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| 型號(hào)： | UC2903QTR |
| 英文描述： | 320 output dot-matrix display driver |
| 中文描述： | 電壓檢測(cè)器 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | UC2903QTR |
5
UC1902
UC2902
UC3902
UNITRODE CORPORATION
7 CONTINENTAL BLVD. MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
The values of five passive components must be deter-
mined to configure the UC3902 load share controller.
The output and return lines of each converter are con-
nected together at the load, with current sense resistor
R
SENSE
inserted in each negative return line. Another re-
sistor, R
ADJ,
is also inserted in each positive remote
sense line. The differential share bus terminals (SHARE+
and SHARE–) of each UC3902 are connected together
respectively, and the SHARE– node is also connected to
the system ground. A typical application is illustrated in
Figure 1.
The load share controller design can be executed by fol-
lowing the next few steps:
Step 1.
(
)
(
)
R
V
A
I
SENSE
SHARE
CSA
O
=
max
max
where A
CSA
is 40, the gain of the current sense amplifier.
At full load, the voltage drop across the R
SENSE
resistor
is I
O
(max) R
SENSE
. Taking into account the gain of the
current sense amplifier, the voltage at full load on the
current share bus,
(
)
V
A
I
SHARE
CSA
O
max
=
This voltage must stay 1.5V below V
CC
or below 10V
whichever is smaller. V
SHARE
represents an upper limit
but the designer should select the full scale share bus
voltage keeping in mind that every volt on the load share
bus will increase the master controller’s supply current by
approximately 100mA times the number of slave units
connected parallel.
(
)
R
SENSE
max
.
Step 2.
(
(
)
)
R
V
I
G
ADJ
ADJ
=
max
max
Care must be taken to ensure that I
ADJ(max)
is low
enough to ensure that both the drive current and power
dissipation are within the UC3902’s capability. For most
applications, an I
ADJ(max)
current between 5mA and
10mA is acceptable. In a typical application, a 360
R
G
resistor from the ADJR pin to ground sets I
ADJ(max)
to
approximately 5mA.
Step 3.
(
I
(
max
)
(
)
RADJ
V
I
R
O
O
SENSE
ADJ
=
max –
max
R
ADJ
must be low enough to not affect the normal opera-
tion of the converter’s voltage feedback loop. Typical
R
ADJ
values are in the 20
to100
range depending on
V
O
,
V
O
(max) and the selected I
ADJ
(max) value.
Step 4.
G
fC
R
G
( )
fC
C
R
R
R
A
A
C
M
ADJ
SENSE
LOAD
CSA
PWR
=
2
π
The share loop compensation capacitor, C
C
is calculated
to produce the desired share loop unity gain crossover
frequency,
fC.
The
share
transconductance, G
M
is nominally 4.5ms. The values of
the resistors are already known. Typically, fC will be set
at least an order of magnitude below the converter’s
closed loop bandwidth. The load share circuit is primarily
intended to compensate for each converter’s initial output
voltage tolerance and temperature drift, not differences in
their transient response. The term A
PWR
(fC) is the gain
of the power supply measured at the desired share loop
crossover frequency, fC. This gain can be measured by
injecting the measurement signal between the positive
output and the positive sense terminal of the power sup-
ply.
loop
error
amplifier’s
Step 5.
R
fC
C
C
C
=
1
2
π
A resistor in series with C
C
is required to boost the phase
margin of the load share loop. The zero is placed at the
load share loop crossover frequency, f
C
.
When the system is powered up, the converter with the
highest output voltage will tend to source the most cur-
rent and take control of the share bus. The other convert-
ers will increase their output voltages until their output
currents are proportional to the share bus voltage minus
50mV. The converter which in functioning as the master
may change due to warmup drift and differences in load
and line transient response of each converter.
ADDITIONAL INFORMATION
Please refer to the following Unitrode topic for additional
application information.
[1] Application Note U-163, The UC3902 Load Share
Controller and Its Performance in Distributed Power Sys-
tems by Laszlo Balogh.
APPLICATION INFORMATION (cont.)
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