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參數(shù)資料
| 型號： | UC2702N |
| 英文描述： | Single channel high side driver with analog current sense for automotive applications |
| 中文描述： | 外圍設備驅動程序| 4驅動器|雙極|雙酯| 16PIN |塑料 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 301K |
| 代理商： | UC2702N |
3
UC1706
UC2706
UC3706
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for T
A
= –55°C to +125°C for
the UC1706, –25°C to +85°C for the UC2706 and 0°C to +70°C for the UC3706; V
IN
= V
C
= 20V. T
A
= T
J
.
PARAMETERS
TEST CONDITIONS
Output High Sat., V
C
-V
O
I
O
= -50mA
MIN
TYP
MAX
2.0
UNITS
V
Output Low Sat., V
O
I
O
= 50mA
I
O
= 500mA
V
REF
= 0.5V
V
REF
= 3.5V
V
REF
= 0
V
CM
= 0 to 15V
V
CM
= 0
0.4
2.5
0.6
3.7
–20
160
–20
V
V
V
V
m
A
mV
m
A
°C
Inhibit Threshold
0.4
3.3
Inhibit Input Current
Analog Threshold
Input Bias Current
Thermal Shutdown
–10
130
–10
155
100
TYPICAL SWITCHING CHARACTERISTICS:
V
IN
= V
C
= 20V, T
A
= 25°C. Delays measured to 10% output change.
PARAMETERS
TEST CONDITIONS
From Inv. Input to Output:
Rise Time Delay
10% to 90% Rise
Fall Time Delay
90% to 10% Fall
From N. I. Input to Output:
Rise Time Delay
10% to 90% Rise
Fall Time Delay
90% to 10% Fall
V
C
Cross-Conduction Current Spike Duration Output Rise
Output Fall
Inhibit Delay
Inhibit Ref. = 1V, Inhibit Inv. = 0.5 to 1.5V
Analog Shutdown Delay
Stop Non-Inv. = 0V, Stop Inv. = 0 to 0.5V
OUTPUT C
L
=
open
110
20
80
25
UNITS
nF
ns
ns
ns
ns
1.0
130
40
90
30
2.2
140
60
110
50
120
20
100
25
25
0
250
180
130
40
120
30
140
60
130
50
ns
ns
ns
ns
ns
ns
ns
ns
CIRCUIT DESCRIPTION
Outputs
The totem-pole outputs have been designed to minimize
cross-conduction current spikes while maximizing fast,
high-current rise and fall times. Current limiting can be
done externally either at the outputs or at the common
V
C
pin. The output diodes included have slow recovery
and should be shunted with high-speed external diodes
when driving high-frequency inductive loads.
Flip/Flop
Grounding pin 7 activates the internal flip-flop to alter-
nate the two outputs. With pin 7 open, the two outputs
operate simultaneously and can be paralleled for higher
current operation. Since the flip-flop is triggered by the
digital input, an off-time of at last 200nsec must be pro-
vided to allow the flip/flop to change states. Note that the
circuit logic is configured such that the “OFF” state is de-
fined as the outputs low.
Digital Inputs
With both an inverting and non-inverting input available,
either active-high or active-low signals may be accepted.
These are true TTL compatible inputs—the threshold is
approximately 1.2V with no hysteresis; and external pull-
up resistors are not required.
Inhibit Circuit
Although it may have other uses, this circuit is included to
eliminate the need for deadband control when driving
relatively slow bipolar power transistors. A diode from
each inhibit input to the opposite power switch collector
will keep one output from turning-on until the other has
turned-off. The threshold is determined by the voltage on
pin 15 which can be set from 0.5 to 3.5V. When this cir-
cuit is not used, ground pin 15 and leave 1 and 16 open.
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