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參數(shù)資料
| 型號(hào)： | UC1874-x |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High Efficiency, Synchronous, Step-down (Buck) Controllers |
| 中文描述： | 高效率，同步，降壓（降壓）控制器 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大?。?/td> | 350K |
| 代理商： | UC1874-X |
5
UC1874-1,-2
UC2874-1,-2
UC3874-1,-2
CAP:
A capacitor is normally connected between this pin
and GND providing bypass for the internal 11V regulator.
Charge is transferred from this capacitor to C
BST
via an
external diode when the low side MOSFET is conducting.
If VCC
≤
10V logic level MOSFETs are generally speci-
fied. CAP should then be shorted to VCC in conjunction
with a low VF Schottky to BOOT to maximize the gate
drive amplitude. This technique provides adequate gate
drive signal amplitudes with VCC as low as 4.5V.
high input voltage applications, a simple external shunt
zener regulator circuit can be connected to CAP, thereby
offloading power dissipation requirements from the IC to
an external transistor.
For
COMP:
This is the output of the voltage amplifier. It pro-
vides the current command signal to the current ampli-
fier. The voltage is clamped to approximately 3.2V.
CT:
A capacitor from CT to GND sets the PWM oscillator
frequency according to the following equation:
1
14250
F
CT
=
Use a high quality ceramic capacitor with low ESL and
ESR for best results. A minimum CT value of 220pF in-
sures good accuracy and less susceptibility to circuit lay-
out parasitics. The oscillator and PWM are designed to
provide practical operation to 300kHZ.
GND:
All voltages are measured with respect to this pin.
All bypass capacitors and timing components except
those listed under the PGND pin description should be
connected to this pin. Component leads should be as
short and direct as possible.
HDRIVE, LDRIVE:
The outputs of the PWM are totem
pole MOSFET gate drivers on the HDRIVE and LDRIVE
pins. The outputs can sink approximately 1A and source
500mA. This characteristic optimizes the switching transi-
tions by providing a controlled dV/dT at turn-on and a
lower impedance at turn-off. These are complementary
outputs with a typical deadtime of 200ns. Internal cir-
cuitry prevents the possibility of simultaneous conduction
of the output MOSFETs (shoot through). HDRIVE is the
high side bootstrapped output. Its upper power supply rail
is the BOOT pin which means that its output will fly ap-
proximately 10V above VCC when the upper side of the
totem pole output is conducting. The power supply rail for
LDRIVE is CAP. As a result the Vgs of both gates are
regulated to approximately 10V if VCC is >11V. A series
resistor between these pins and the MOSFET gates of at
least 10 ohms can be used to control ringing. Addition-
ally, a low VF Schottky diode should be connected be-
tween
these
pins
and
GND
conduction and possible erratic operation.
to
prevent
substrate
ISNS-:
This is the inverting input to the X10 instrumenta-
tion amplifier. The common mode input range for this pin
extends from GND to VCC. A low value resistor in series
with the output inductor is connected between this pin
and ISNS+ to develop the current sense signal.
ISNS+:
This is the non-inverting input to the X10 instru-
mentation amplifier. The common mode input range for
this pin extends from GND to VCC.
ISOUT:
This is the output of the X10 instrumentation am-
plifier. The output voltage on this pin is level shifted 2V
above GND, such that if a 100mV differential input is ap-
plied across ISNS+ and ISNS-, the output will be 3V.
PGND:
This is the high current ground for the IC. The
MOSFET driver transistors are referenced to this ground.
For best performance an external star ground connection
should be made between this pin, the source of the low
side MOSFET, the capacitor on CAP, the anodes of any
external Schottky clamp diodes and the output filter ca-
pacitor. As with all high frequency layouts, a ground
plane and short leads are highly recommended.
SB:
The voltage on SB sets the output current level at
which standby mode is initiated. A voltage level from 0V
to 1V programs the threshold from 50% to 0% of full load
current. Full load current corresponds to a 100mV differ-
ential signal across the ISNS inputs. Since this is a
high impedance input, a voltage divider derived from
VREF may be used to program this level. Another possi-
ble use is to actively control this level with external cir-
cuitry to adaptively control converter efficiency. Tying SB
to VREF disables standby mode operation.
SS:
A capacitor from this pin to GND in conjunction with
an internal 10mA current source provides a soft start
function for the IC. The voltage level on SS clamps the
output of the voltage amplifier through an internal buffer,
thus providing a controlled startup. The SS time is ap-
proximately:
V
V
A
10
μ
C
V
SS
O
IN
3
Once the device has completed its soft start cycle, a low
power sleep mode can be invoked by pulling SS below
0.5V typically. In sleep mode, all of the device functions
are disabled except for those which are required to bring
the device out of sleep mode when SS is released. Typi-
cal sleep mode supply current is less than 50mA.
VCC:
Positive supply rail for the IC. Bypass this pin to
GND with a 1mF low ESL/ESR ceramic capacitor. The
maximum voltage for VCC is 36V. The turn on voltage
level on VCC is 4.5V with 100mV of hysteresis for the
UC3874-1 and 10V with 1V of hysteresis for the
UC3874-2.
相關(guān)PDF資料 |
PDF描述 |
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| UC3874L-2 | High Efficiency, Synchronous, Step-down Buck Controllers |
| UC3874 | High Efficiency, Synchronous, Step-down (Buck) Controllers |
| UC3874Q-1 | High Efficiency, Synchronous, Step-down Buck Controllers |
| UC3874Q-2 | High Efficiency, Synchronous, Step-down Buck Controllers |
| UC2874 | High Efficiency, Synchronous, Step-down (Buck) Controllers |
相關(guān)代理商/技術(shù)參數(shù) |
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| UC1875 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Phase Shift Resonant Controller |
| UC1875 DIE | 制造商:Texas Instruments 功能描述: |
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| UC1875J | 制造商:Texas Instruments 功能描述:Soft Sw PWM Cntrlr 4-OUT PH SHIFT RES 1MHz 20-Pin CDIP Tube 制造商:Texas Instruments 功能描述:SOFT SW PWM CNTRLR 4-OUT PH SHIFT RES 1MHZ 20CDIP - Rail/Tube |
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