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參數(shù)資料
| 型號(hào)： | UC1845AY |
| 英文描述： | Digital controlled stereo audio processor |
| 中文描述： | 電流模式開關(guān)電源控制器 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 463K |
| 代理商： | UC1845AY |
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
Current Mode PWM Controller
FEATURES
Optimized For Off-line And DC
To DC Converters
Low Start Up Current (<1mA)
Automatic Feed Forward
Compensation
Pulse-by-pulse Current Limiting
Enhanced Load Response
Characteristics
Under-voltage Lockout With
Hysteresis
Double Pulse Suppression
High Current Totem Pole
Output
Internally Trimmed Bandgap
Reference
500khz Operation
Low R
O
Error Amp
DESCRIPTION
The UC1842/3/4/5 family of control ICs provides the necessary features to im-
plement off-line or DC to DC fixed frequency current mode control schemes
with a minimal external parts count. Internally implemented circuits include un-
der-voltage lockout featuring start up current less than 1mA, a precision refer-
ence trimmed for accuracy at the error amp input, logic to insure latched
operation, a PWM comparator which also provides current limit control, and a
totem pole output stage designed to source or sink high peak current. The out-
put stage, suitable for driving N Channel MOSFETs, is low in the off state.
Differences between members of this family are the under-voltage lockout
thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have
UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applica-
tions. The corresponding thresholds for the UC1843 and UC1845 are 8.4V
and 7.6V. The UC1842 and UC1843 can operate to duty cycles approaching
100%. A range of zero to 50% is obtained by the UC1844 and UC1845 by the
addition of an internal toggle flip flop which blanks the output off every other
clock cycle.
BLOCK DIAGRAM
A/B
Note 1: A = DIL-8 Pin Number. B = SO-14 Pin Number.
Note 2: Toggle flip flop used only in 1844 and 1845.
4/97
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