參數(shù)資料
型號: UC1844DTR
英文描述: Digital controlled stereo audio processor with loudness
中文描述: 開關(guān)電源控制器
文件頁數(shù): 6/8頁
文件大?。?/td> 576K
代理商: UC1844DTR
6
High peak currents associated with capacitive loads ne-
cessitate careful grounding techniques. Timing and by-
pass capacitors should be connected close to pin 5 in a
single point ground. The transistor and 5k potentiometer
are used to sample the oscillator waveform and apply
an adjustable ramp to pin 3.
Shutdown of the UC1842 can be accomplished by two
methods; either raise pin 3 above 1V or pull pin 1 below
a voltage two diode drops above ground. Either method
causes the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset domi-
nant so that the output will remain low until the next
clock cycle after the shutdown condition at pin 1 and/or
3 is removed. In one example, an externally latched
shutdown may be accomplished by adding an SCR
which will be reset by cycling V
CC
below the lower
UVLO threshold. At this point the reference turns off, al-
lowing the SCR to reset.
UC1842/3/4/5
UC2842/3/4/5
OUTPUT SATURATION CHARACTERISTICS
ERROR AMPLIFIER OPEN-LOOP
FREQUENCY RESPONSE
OPEN-LOOP LABORATORY FIXTURE
SHUT DOWN TECHNIQUES
相關(guān)PDF資料
PDF描述
UC1844N Digital controlled stereo audio processor with loudness
UC1844Q Digital controlled stereo audio processor with loudness
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