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| 型號： | UC1682THCZ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HIGH-VOLTAGE MIXED-SIGNAL IC |
| 中文描述： | 高電壓混合信號集成電路 |
| 文件頁數(shù)： | 34/70頁 |
| 文件大小： | 1161K |
| 代理商： | UC1682THCZ |
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U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
1999 ~
2003
32
ES Specifications
LCD D
ISPLAY
C
ONTROLS
C
LOCK
& T
IMING
G
ENERATOR
UC1682 contains a built-in system clock. All
required components for the clock oscillator are
built-in. No external parts are required.
Four different line rates are provided for system
design flexibility. The line rate is controlled by
register LC[4:3]. When Mux-Rate is above 38,
frame rate is calculated as:
Frame Rate = Line-Rate / Mux-Rate.
When Mux-Rate is lowered to 38 (and 24), line
rate will be scaled down by 2 (and 3) times
automatically reduce power consumption.
Flicker-free frame rate is dependent on LC
material and gray-shade modulation scheme.
Frame rate 175Hz is recommended for 32-shade
mode. Choose lower frame rate for lower power,
and choose higher frame rate to improve LCD
contrast and minimize flicker.
When switching from 32-shade modulation to 8-
shade modulation, line rate will be scaled down
automatically by ~30%. Under most situations,
flicker behavior is similar between these two
different modulation schemes.
When switching from 32-shade modulation to 8-
shade modulation, line rate will be scaled down
automatically by ~35%. Under most situations,
flicker behavior is similar between these two
different modulation schemes. However, it is
always recommended to test each mode to make
sure flicker behavior is acceptable
D
RIVER
M
ODES
COM and SEG drivers can be in either Idle mode
or Active mode, controlled by Display Enable flag
(DC[2]). When SEG drivers are in Idle mode, they
will be connected together to ensure zero DC
condition on the LCD.
D
RIVER
A
RRANGEMENTS
The naming conventions are: COM(x), where
x=1~80, refers to the COM driver for the x-th row
of pixels on the LCD panel.
The mapping of COM(x) to LCD pixel rows is
fixed and it is not affected by SL, CST, CEN, DST,
DEN, MX or MY settings.
D
ISPLAY
C
ONTROLS
There are three groups of display control flags in
the control register DC: Driver Enable (DE), All-
Pixel-ON (APO) and Inverse (PXV). DE has the
overriding effect over PXV and APO.
D
RIVER
E
NABLE
(DE)
Driver Enable is controlled by the value of DC[2]
via
Set Display Enable
command. When DC[2] is
set to OFF (logic “0”), both COM and SEG drivers
will become idle and UC1682 will put itself into
Sleep mode to conserve power.
When DC[2] is set to ON, the DE flag will become
“1”, and UC1682 will first exit from Sleep mode,
restore the power (V
LCD
, V
D
etc.) and then turn on
COM and SEG drivers.
A
LL
P
IXELS
O
N
(APO)
When set, this flag will force all SEG drivers to
output ON signals, disregarding the data stored
in the display buffer.
This flag has no effect when Display Enable is
OFF and it has no effect on data stored in RAM.
I
NVERSE
(PXV)
When this flag is set to ON, SEG drivers will
output the inverse of the value it received from
the display buffer RAM (bit-wise inversion). This
flag has no impact on data stored in RAM.
P
ARTIAL
S
CROLL
Control register FL specifies a region of rows
which are not affected by the SL register. Since
SL register can be used to implement scroll
function. The FL register can be used to
implement fixed region when the other part of the
display is scrolled by SL.
P
ARTIAL
D
ISPLAY
UC1682 provides flexible control of Mux Rate
and active display area. Please refer to command
Set COM End, Set Partial Display Start
, and
Set
Partial Display
End
for more detail.
G
RAY
-
SHADE
M
ODULATION
M
ODE
UC1682 has two gray-shade modulation modes:
32-shade and 8-shade.
The 8-shade mode will consume ~30% less
power than the 32-shade mode, and can be used
for situations where power consumption is more
critical than color fidelity.
Changing gray-shade modulation mode does not
affect the content of SRAM display buffer, and
the image data will remain the same after
switching back and forth between 8-shade mode
and 32-shade mode.
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