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參數(shù)資料
| 型號： | UA2 |
| 英文描述： | Input/output rail-to-rail low power operational amplifier |
| 中文描述： | UA2初步[更新10/01。 8頁]超低價的FPGA轉換 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 112K |
| 代理商： | UA2 |
3
UA2
Rev. A
–
29-Oct-01
In order to improve noise immunity within the device, separate V
DD
and V
SS
busses are
provided for the internal cells and the I/O cells.
I/O buffer interfacing
I/O Flexibility
All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A
level translator could be located close to each buffer.
I/O Options
Inputs
Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull
up or pull down resistor.
Fast Output Buffer
Fast output buffers are able to source or sink 2 to 18mA at 3.3V according to the chosen
option. 36mA achievable, using 2 pads.
Slew Rate Controlled Output Buffer
In this mode, the p
–
and n
–
output transistors commands are delayed, so that they are
never set
“
ON
”
simultaneously, resulting in a low switching current and low noise. These
buffers are dedicated to very high load drive.
2.5V Compatibility
The UA2 series of ULC
’
s is fully capable of supporting high
–
performance operation at
2.5V for core or 3.3V for periphery. The performance specifications of any given ULC
design however, must be explicitly specified as 2.5V, 3.3V or both.
Power Supply and Noise Protection
The speed and density of the UA2 technology cause large switching current spikes, for
example, when:
16 high current output buffers switch simultaneously, or
10% of the 700 000 gates are switching within a window of 1ns.
Sharp edges and high currents cause some parasitic elements in the packaging to
become significant. In this frequency range, the package inductance and series resis-
tance should be taken into account. It is known that an inductor slows down the setting
time of the current and causes voltage drops on the power supply lines. These drops
can affect the behavior of the circuit itself or disturb the external application (ground
bounce).
In order to improve the noise immunity of the UA2 core matrix, several mechanisms
have been implemented inside the UA2 arrays. Two types of protection have been
added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers
against the switching noise coming from the matrix.
I/O buffers switching protection
Three features are implemented to limit the noise generated by the switching current:
The power supplies of the input and output buffers are separated.
The rise and fall times of the output buffers can be controlled by an internal
regulator.
A design rule concerning the number of buffers connected on the same power
supply line has been imposed.
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