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參數(shù)資料
| 型號： | U637H256 |
| 英文描述： | CapStore 32K x 8 nvSRAM |
| 中文描述： | CapStore 32K的× 8非易失 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 158K |
| 代理商： | U637H256 |
U637H256
4
August 15, 2006
STK Control #ML0056
Rev 1.1
DC Characteristics
Symbol
Conditions
C-Type
K-Type
Unit
Min.
Max.
Min.
Max.
Output High Voltage
Output Low Voltage
V
OH
V
OL
V
CC
I
OH
I
OL
= 4.5 V
=-4 mA
= 8 mA
2.4
0.4
2.4
0.4
V
V
Output High Current
Output Low Current
I
OH
I
OL
V
CC
V
OH
V
OL
= 4.5 V
= 2.4 V
= 0.4 V
8
-4
8
-4
mA
mA
Input Leakage Current
High
Low
I
IH
I
IL
V
CC
V
IH
V
IL
= 5.5 V
= 5.5 V
= 0 V
-1
1
-1
1
μ
A
μ
A
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
V
CC
V
OH
V
OL
= 5.5 V
= 5.5 V
= 0 V
-1
1
-1
1
μ
A
μ
A
SRAM Memory Operations
No.Switching Characteristics
Read Cycle
Symbol
Min.
Max.
Unit
Alt.
IEC
1
Read Cycle Time
f
t
AVAV
t
cR
25
ns
2
Address Access Time to Data Valid
g
t
AVQV
t
a(A)
25
ns
3
Chip Enable Access Time to Data Valid
t
ELQV
t
a(E)
25
ns
4
Output Enable Access Time to Data Valid
t
GLQV
t
a(G)
10
ns
5
E HIGH to Output in High-Z
h
t
EHQZ
t
dis(E)
10
ns
6
G HIGH to Output in High-Z
h
t
GHQZ
t
dis(G)
10
ns
7
E LOW to Output in Low-Z
t
ELQX
t
en(E)
5
ns
8
G LOW to Output in Low-Z
t
GLQX
t
en(G)
0
ns
9
Output Hold Time after Address Change
t
AXQX
t
v(A)
3
ns
10 Chip Enable to Power Active
e
t
ELICCH
t
PU
0
ns
11 Chip Disable to Power Standby
d, e
t
EHICCL
t
PD
25
ns
e:
f:
g:
h:
Parameter guaranteed but not tested.
Device is continuously selected with E and G both Low.
Address valid prior to or coincident with E transition LOW.
Measured
±
200 mV from steady state output voltage.
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