參數(shù)資料
型號: U634H256S2K35G1
英文描述: PowerStore 32K x 8 nvSRAM
中文描述: PowerStore 32K的× 8非易失
文件頁數(shù): 13/15頁
文件大?。?/td> 229K
代理商: U634H256S2K35G1
U634H256
13
August 15, 2006
STK Control #ML0048
Rev 1.1
Low Average Active Power
The U634H256 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the power supply voltage level
+
0.1
μ
F
Bypass
100
μ
F
±
20 %
V
CAP
V
SS
Power
Supply
V
CCX
HSB
10 k
Ω
(optional,
see description HSB
nonvolatile store)
Figure 1: Automatic STORE Operation
Schematic Diagram
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
32
31
30
2
3
4
5
6
7
8
9
10
11
29
28
27
26
25
24
23
22
12
13
14
15
16
21
20
19
18
17
V
CAP
5.0 V
V
SWITCH
STORE inhibit
Power Up
RECALL
t
RESTORE
(24)
t
Disabling Automatic STORES: STORE Cycle Inhibit and Automatic Power Up RECALL
1
0.1
μ
F
Bypass
V
CAP
V
SS
Power
Supply
V
CCX
HSB
10 k
Ω
(optional,
see description HSB
nonvolatile store)
Figure 2: Disabling Automatic STORES
Schematic Diagram
32
31
30
2
3
4
5
6
7
8
9
10
11
29
28
27
26
25
24
23
22
12
13
14
15
16
21
20
19
18
17
1
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相關代理商/技術參數(shù)
參數(shù)描述
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