參數(shù)資料
型號: U631H64BDC45
英文描述: General purpose JFET quad operational amplifiers
中文描述: NVRAM中(EEPROM的基礎(chǔ))
文件頁數(shù): 7/12頁
文件大?。?/td> 125K
代理商: U631H64BDC45
7
November 01, 2001
U631H64
No.STORE Cycle Inhibit and
Automatic Power Up RECALL
Symbol
Min.
Max.
Unit
Alt.
IEC
24 Power Up RECALL Duration
k, e
t
RESTORE
650
μ
s
Low Voltage Trigger Level
V
SWITCH
4.0
4.5
V
Nonvolatile Memory Operations
STORE Cycle Inhibit and Automatic Up RECALL
k:
t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
V
CC
5.0 V
V
SWITCH
STORE inhibit
Power Up
RECALL
t
RESTORE
(24)
t
Software Mode Selection
E
W
A12 - A0
(hex)
Mode
I/O
Power
Notes
L
H
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
I
CC2
l, m
l, m
l, m
l, m
l, m
l
L
H
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l
l:
The six consecutive addresses must be in order listed (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a Store cycle or (0000, 1555, 0AAA,
1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and
diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0000, 1555, 0AAA, 1FFF, 10F0, 139C.
m: I/O state assumes that G
V
IL
. Activation of nonvolatile cycles does not depend on the state of G.
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