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參數(shù)資料
| 型號： | U630H64SK25 |
| 英文描述： | Low noise JFET quad operational amplifier |
| 中文描述： | NVRAM中（EEPROM的基礎(chǔ)） |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 143K |
| 代理商： | U630H64SK25 |
12
November 01, 2001
U630H64
Device Operation
The U630H64 has two separate modes of operation:
SRAM mode and nonvolatile mode, determined by the
state of the NE pin. In SRAM mode, the memory opera-
tes as a standard fast static RAM. In nonvolatile mode,
data is transferred from SRAM to EEPROM (the
STORE operation) or from EEPROM to SRAM (the
RECALL operation). In this mode SRAM functions are
disabled.
SRAM READ
The U630H64 performs a READ cycle whenever E and
G are LOW while W and NE are HIGH. The address
specified on pins A0 - A12 determines which of the
8192 data bytes will be accessed. When the READ is
initiated by an address transition, the outputs will be
valid after a delay of t
cR
. If the READ is initiated by E or
G, the outputs will be valid at t
a(E)
or at t
a(G)
, whichever
is later. The data outputs will repeatedly respond to
address changes within the t
cR
access time without the
need for transition on any control input pins, and will
remain valid until another address change or until E or
G is brought HIGH or W or NE is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW and NE is HIGH. The address inputs must be sta-
ble prior to entering the WRITE cycle and must remain
stable until either E or W goes HIGH at the end of the
cycle. The data on pins DQ0 - 7 will be written into the
memory if it is valid t
su(D)
before the end of a W control-
led WRITE or t
su(D)
before the end of an E controlled
WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers t
dis (W)
after W goes LOW.
Noise Consideration
The U630H64 is a high speed memory and therefore
must have a high frequency bypass capacitor of appro-
ximately 0.1
μ
F connected between V
CC
and V
SS
using
leads and traces that are as short as possible. As with
all high speed CMOS ICs, normal carefull routing of
power, ground and signals will help prevent noise
problems.
Hardware Nonvolatile STORE
A STORE cycle is performed when NE, E and W are
LOW while G is HIGH. While any sequence to achieve
this state will initiate a STORE, only W initiation and E
initiation are practical without risking an unintentional
SRAM WRITE that would disturb SRAM data. During a
STORE cycle, previous nonvolatile data is erased and
the SRAM contents are then programmed into nonvola-
tile elements. Once a STORE cycle is initiated, further
input and output is disabled and the DQ0 - 7 pins are
tristated until the cycle is completed.
If E and G are LOW and W and NE are HIGH at the
end of the cycle, a READ will be performed and the out-
puts will go active, indicating the end of the STORE.
Hardware Nonvolatile RECALL
A RECALL cycle is performed when E, G and NE are
LOW while W is HIGH. Like the STORE cycle, RECALL
is initiated when the last of the three clock-signals goes
to the RECALL state. Once initiated, the RECALL cycle
will take RECALL Cycle Time“ to complete, during
which all inputs are ignored. When the RECALL com-
pletes, any READ or WRITE state on the input pins will
take effect.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL in no way alters the data in the nonvolatile
cells. The nonvolatile data can be recalled an unlimited
number of times.
Like the STORE cycle, a transition must occur on some
control pins to cause a RECALL, preventing inadver-
tend multi-triggering.
Automatic Power Up RECALL
On power up, once V
CC
exceeds the sense voltage of
V
SWITCH
, a RECALL cycle is automatically initiated. The
voltage on the V
CC
pin must not drop below V
SWITCH
once it has risen above it in order for the RECALL to
operate properly. Due to this automatic RECALL,
SRAM operation cannot commence until t
RESTORE
after
V
CC
exceeds V
SWITCH
. If the U630H64 is in a WRITE
state at the end of power up RECALL, the SRAM data
will be corrupted.
To help avoid this situation, a 10 K
resistor should be
connected between W and system V
CC
.
Hardware Protection
The U630H64 offers two levels of protection to sup-
press inadvertent STORE cycles. If the control signals
(E, G, W and NE) remain in the STORE condition at the
end of a STORE cycle, a second STORE cycle will not
be started. The STORE (or RECALL) will be initiated
only after a transition on any one of these signals to the
required state. In addition to multi-trigger protection, the
U630H64 offers hardware protection through V
CC
Sense. When V
CC
< V
SWITCH
the externally initiated
STORE operation will be inhibited.
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PDF描述 |
|---|---|
| U630H64SK35 | NVRAM (EEPROM Based) |
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| U631H64BDC25 | General purpose JFET quad operational amplifiers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| U630H64SK35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U630H64SK45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U631 | 功能描述:開關(guān)配件 PushButton Cap Blue RoHS:否 制造商:C&K Components 類型:Cap 用于:Pushbutton Switches 設(shè)計目的: |
| U631H16 | 制造商:SIMTEK 制造商全稱:Simtek Corporation 功能描述:SimtekSoftStore 2K x 8 nvSRAM |
| U631H16BD1C25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SOFTSTORE 2K X 8 NVSRAM |
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