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參數(shù)資料
| 型號： | U630H64DK35 |
| 英文描述： | Low noise JFET dual operational amplifiers |
| 中文描述： | NVRAM中（EEPROM的基礎(chǔ)） |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 143K |
| 代理商： | U630H64DK35 |
10
November 01, 2001
U630H64
t
su(N)R
t
su(W)R
t
w(G)R
t
d(G)R
High Impedance
(48)
(47)
(49)
(50)
(46)
NE
G
W
E
DQi
Output
t
su(E)R
No.
RECALL Cycle G-controlled
Symbol
Min.
Max.
Unit
Alt.
IEC
46
RECALL Cycle Time
t
GLQXR
t
d(G)R
20
μ
s
47
RECALL Initiation Cycle Time
t
GLNH
t
w(G)R
25
ns
48
NE Setup
t
NLGL
t
su(N)R
5
ns
49
Write Enable Setup
t
WHGL
t
su(W)R
5
ns
50
Chip Enable Setup
t
ELGL
t
su(E)R
5
ns
RECALL Cycle: G-controlled
o, r
m: Measured with W and NE both returned HIGH, and G returned LOW. Note that STORE cycles are
inhibited/aborted by V
CC
< V
SWITCH
(STORE inhibit).
n:
Once t
w(W)S
has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W and E may be used to
terminate the STORE initiation cycle.
o:
If E is LOW for any period of time in which W is HIGH while G and NE are LOW, than a RECALL cycle may be initiated.
For E-controlled STORE during t
w(E)S
W, G, NE have to be static.
p:
Measured with W and NE both HIGH, and G and E LOW.
q:
Once t
w(N)R
has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to
terminate the RECALL initiation cycle.
r:
If W is LOW at any point in which both E and NE are LOW and G is HIGH, than a STORE cycle will be initiated instead of a RECALL.
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| U630H64DK45 | NVRAM (EEPROM Based) |
| U630H64SC25 | Low noise JFET quad operational amplifier |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| U630H64DK45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U630H64SC25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U630H64SC35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U630H64SC45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U630H64SK25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
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