參數(shù)資料
型號(hào): U62256ADC07LLG1
廠商: Electronic Theatre Controls, Inc.
英文描述: STANDARD 32K X 8 SRAM
中文描述: 32K的標(biāo)準(zhǔn)× 8的SRAM
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 164K
代理商: U62256ADC07LLG1
U62256A
April 20, 2004
5
Switching Characteristics
Read Cycle
Symbol
07
10
Unit
Alt.
IEC
Min.
Max.
Min.
Max.
Read Cycle Time
t
RC
t
cR
70
100
ns
Address Access Time to Data Valid
t
AA
t
a(A)
70
100
ns
Chip Enable Access Time to Data Valid
t
ACE
t
a(E)
70
100
ns
Output Enable Access Time to Data Valid
t
OE
t
a(G)
35
45
ns
E HIGH to Output in High-Z
t
HZCE
t
dis(E)
25
35
ns
G HIGH to Output in High-Z
t
HZOE
t
dis(G)
25
35
ns
E LOW to Output in Low-Z
t
LZCE
t
en(E)
5
5
ns
G LOW to Output in Low-Z
t
LZOE
t
en(G)
0
0
ns
Output Hold Time from Address Change
t
OH
t
v(A)
5
5
ns
Switching Characteristics
Write Cycle
Symbol
07
10
Unit
Alt.
IEC
Min.
Max.
Min.
Max.
Write Cycle Time
t
WC
t
cW
70
100
ns
Write Pulse Width
t
WP
t
w(W)
55
70
ns
Write Pulse Width Setup Time
t
WP
t
su(W)
55
70
ns
Address Setup Time
t
AS
t
su(A)
0
0
ns
Address Valid to End of Write
t
AW
t
su(A-WH)
65
80
ns
Chip Enable Setup Time
t
CW
t
su(E)
65
80
ns
Pulse Width Chip Enable to End of Write
t
CW
t
w(E)
65
80
ns
Data Setup Time
t
DS
t
su(D)
30
35
ns
Data Hold Time
t
DH
t
h(D)
0
0
ns
Address Hold from End of Write
t
AH
t
h(A)
0
0
ns
W LOW to Output in High-Z
t
HZWE
t
dis(W)
25
35
ns
G HIGH to Output in High-Z
t
HZOE
t
dis(G)
25
35
ns
W HIGH to Output in Low-Z
t
LZWE
t
en(W)
0
0
ns
G LOW to Output in Low-Z
t
LZOE
t
en(G)
0
0
ns
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