參數(shù)資料
型號: U490B
英文描述: One-Shot Phase Control
中文描述: 一次性相位控制
文件頁數(shù): 2/6頁
文件大?。?/td> 84K
代理商: U490B
U490B
TELEFUNKEN Semiconductors
Rev. A1, 29-May-96
2 (6)
Pin Description
1
2
3
4
5
6
7
8
NC
Trigger
Sync.
GND
V
S
Ramp
Output
Contr
Pin
1
2
3
4
5
6
7
8
Symbol
NC
Trigger
Sync.
GND
Contr
Ramp
Output
V
S
Function
Not connected
Triggering
Synchronization
Ground
Control input
Ramp
Output
Supply voltage
Supply, Pin 8
Internal voltage limiter enables a simple supply from the
mains via series resistor R
1
.The supply voltage between
Pin 8 (V
S
) and ground (Pin 4) builts up via R
1
and is
smoothed by the capacitor C
1.
Series resistor R
1
can be calculated as follows:
0.85 xV
mains
– V
Smax
2 x I
tot
R
1max
where
V
mains
V
Smax
I
tot
I
Smax
I
X
Mains supply voltage
Maximum supply voltage
I
Smax
I
X
Maximum current consumption of the IC
Current consumption of the
external components
Phase Control, Pins 3, 5 and 6
The circuit is synchronized with mains supply through
Pin 3. As long as the switch S
1
is open, the circuit is in
wait state i.e., the capacitor C
6
(150 nF) is discharged and
is kept in this state (High level). When the switch S
1
is
closed, there is a current flow in Pin 2 which is evaluated
by the circuit. If this current flows after the elapse of delay
time, then the phase control is released. Capacitor, C
6
, is
then charged with I
6
100 A towards ground. At the
same time, there is a current flow of
which results in voltage drop across resistor R
5
. Control
voltage, V
5
, is then 1.5 V lower internally.
The output stage is released when the ramp voltage V
6
is
equal to (V
5
1.5 V). When the voltage difference is
150 mV, it is again turned–off.
100 A into Pin 5,
The result is an output pulse, whose phase shift to the zero
crossing of mains voltage is determined by the resistor R
5
at control input Pin 5 (see fig. 2). Capacitor C
6
is charged
to a value of
1.5 V. It remains there till the switch S
1
again opens and the repetition delay time is over.
The circuit is released, when four periods of the line volt-
age have expired after build up of the operating voltage,
before the switch S
1
is closed.
closed
open
V
8
V
8
S
1
V
(Sync.)
V
2
(Trigger)
V
(Ramp)
(Output)
0
50 ms
100 ms
t
1
150 ms
200 ms
t
V
6
V
7
t
150 mV
”X”
”X”
95 10867
V
5
– 1.5 V
V
t
p
Figure 2. Signal characteristics
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