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參數資料
| 型號： | U3500BM-BFLG3 |
| 英文描述： | Cordless Telephone Signal Processor |
| 中文描述： | 無繩電話信號處理器 |
| 文件頁數： | 11/17頁 |
| 文件大小： | 230K |
| 代理商： | U3500BM-BFLG3 |
U3500BM
Preliminary Information
Rev. A3, 20-May-98
11 (17)
F–3 dB=3.35 kHz
Signal: 4.1 kHz/DC/OFF
State : SCRON/SCROFF/DATA
Gain : –4 dB/0 dB/OFF
F–3 dB=3.95 kHz
Signal: 1 kHz
State : SCRON/SCROFF
Gain : 5.9 dB/1.9 dB
F–3 dB=3.95 kHz
Signal: 4.1 kHz/DC/OFF
State : DESCRON/DESCROFF/DATA
Gain : –4 dB/0 dB/OFF
F–3 dB=3.35 kHz
Signal: 1 kHz
State : DESCRON/DESCROFF
Gain : –0.5 dB/–4.5 dB
DATA
Output buffer
Deemphasis
11786
F–3 dB=1 kHz
DATA
Comparator
RGAIN
ADJ
F–3 dB=90 Hz
Gain stage
Demo–
dulator
Figure 11.
Serial Bus Interface
The circuit is remoted by an external microcontroller
through the serial bus (programming can be started 10 s
after power supply settled).
The data is an 12-bit word:
A3 – A0: address of the destination register (0 to 15)
D7 – D0: contents of register
The data line must be stable when the clock is high and
data must be serially shifted.
After 12 clock periods, the transfer to the destination reg-
ister is (internally) generated by a low-to-high transition
of the data line when the clock is high.
Micro-
processor
D
Clock
C
96 11787
Data
Figure 12.
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