參數(shù)資料
型號(hào)： U2733B-C
英文描述： Fractional-N Frequency Synthesizer for DAB Tuner
中文描述： 分?jǐn)?shù)N頻率合成器的DAB調(diào)諧器
文件頁(yè)數(shù)： 1/14頁(yè)
文件大?。?/td> 157K
代理商： U2733B-C
U2733B-C
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 21-Aug-96
1 (14)
Fractional-N Frequency Synthesizer for DAB Tuner
Description
The
U2733B-C
fractional-N frequency synthesizer circuit fabricated in
TEMIC’s advanced UHF5S technology. Designed for
applications in DAB receivers, it controls a VCO to
synthesize frequencies in the range of 70 to 500 MHz in
a 16 kHz raster; four different reference divide factors can
is
a
monolithically
integrated
be selected. The lock status of the phase detector is
indicated at a special output pin, six switching outputs can
be addressed. An internal frequency doubler provides an
output signal having twice the frequency of the reference
oscillator. All functions of this IC are controlled by
I
2
C bus.
Features
Microprocessor controlled via I
2
C bus
4 addresses selectable
Four reference divide factors selectable:
1024, 1120, 1152, 1536
Effectively
Programmable 15-bit counter 1:2048 to 1:32767
effectively
Three state phase detector with programmable charge
pump
Superior phase noise performance
Deactivation of tuning output programmable
6 switching outputs (open collector)
Reference frequency doubler (open collector output)
Lock status indication (open collector)
Fully compatible to U2753B-C
SSO20 package
Block Diagram
Reference counter
19
20
11
12
13
14
15
6
7
8
4
NREF
5
18
17
RF
NRF
PLCK
PD
VD
3
1
2
I2C Bus –Interface / Control
REF
9
16
Frequency doubler
x 2
FDO
10
NFDO
N/N=1
Fractional N
control
Prog.
13 Bit counter
2 Bit
latch
5 Bit latch
Three State
Phase
Detector
Lock detector
Prog.
charge pump
4 Bit latch
7 Bit latch
MUX
MUX
Switches
SWC SWD SWE SWF SWG SWH
GND
VS
ADR
SCL
SDA
12476
Figure 1. Block diagram
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