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參數(shù)資料
| 型號(hào)： | U1898 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 小信號(hào)晶體管 |
| 英文描述： | N-Channel Switch |
| 中文描述： | N-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-92 |
| 封裝： | TO-92, 3 PIN |
| 文件頁(yè)數(shù)： | 1/3頁(yè) |
| 文件大?。?/td> | 26K |
| 代理商： | U1898 |
2004 Fairchild Semiconductor Corporation
Rev. A, April 2004
U
Absolute Maximum Ratings*
T
a
=25
°
C unless otherwise noted
Symbol
V
DG
Drain-Gate Voltage
V
GS
Gate-Source Voltage
I
GF
Forward Gate Current
T
J
, T
STG
Operating and Storage Junction Temperature Range
* This ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These rating are based on a maximum junction temperature of 150 degrees C.
2) These are steady limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Electrical Characteristics
T
a
=25
°
C unless otherwise noted
Symbol
Parameter
Off Characteristics
V
(BR)GS
Gate-Source Breakdown Voltage
V
GS(off)
Gate-Source Cutoff Voltage
I
DGO
Drain-Gate Leakage Current
On Characteristics
I
DSS
Zero-Gate Voltage Drain Current *
r
DS(on)
Small Signal Characteristics
r
ds(on)
Drain-Source On Resistance
C
iss
Input Capacitance
C
rss
Reverse Transfer Capacitance
Switching Characteristics
t
on
Turn-On Time
t
off
Turn-Off Time
* Pulse Test: Pulse Width
≤
300
μ
s, Duty Cycle
≤
2.0%
Thermal Characteristics
T
a
=25
°
C unless otherwise noted
Symbol
P
D
Total Device Dissipation
Derate above 25
°
C
R
θ
JC
Thermal Resistance, Junction to Case
R
θ
JA
Thermal Resistance, Junction to Ambient
Parameter
Ratings
40
-40
50
-55 ~ 150
Units
V
V
mA
°
C
Test Condition
Min.
Max.
Units
I
G
= 1.0
μ
A, V
DS
= 0
V
DS
= 20 V, I
D
= 1.0 nA
V
DG
= 20 V, I
S
= 0
-40
-2.0
V
V
pA
-7.0
-200
V
DS
= 20 V, V
GS
= 0
I
D
= 1.0 mA, V
GS
= 0
15
mA
50
V
DS
= VGS = 0, f= 1.0 kHz
V
DS
= 20, V
GS
= 0, f = 1.0 MHz
V
GS
= - 20 V, f = 1.0 MHz
50
16
5.0
pF
pF
I
D(on)
= 6.0 mA
V
GS(off)
= 6.0 V
35
60
ns
ns
Parameter
Max.
625
5.0
125
357
Units
mW
mW/
°
C
°
C/W
°
C/W
U1898
N-Channel Switch
This device is designed for low level analog switching, sample and
hold circuits and chopper stabalized amplifiers.
Sourced from Process 51.
See J111 for characteristics.
TO-92
1. Drain 2. Source 3. Gate
1
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