參數(shù)資料
型號(hào): TZA3001
廠商: NXP Semiconductors N.V.
元件分類: XO, clock
英文描述: SDH/SONET data and clock recovery unit STM1/4 OC3/12
中文描述: SDH / SONET的數(shù)據(jù)和時(shí)鐘恢復(fù)單元STM1 / 4 OC3/12
文件頁(yè)數(shù): 20/54頁(yè)
文件大小: 1852K
代理商: TZA3001
20
Fiber optic transceiver board STM1/4/8,
OC3,12,24, FC/GE
Philips Semiconductors
Application Note
AN98090
2.2
Layout considerations
The layout for the demoboard is designed on a 4 layer PCB. The layers are numbered: top layer 1, bottom layer
2, buried layer top 3 and buried layer bottom 4. The copper on the layers is 35
μ
m thick, the space between the
layers is 0.435 and 0.5 mm. The material is FR4, with relative dielectric constant
ε
r
=4.3. No buried via’s are
used. The use of the layers is ordered as follows (from top to bottom)
Layer 1, top: Signal
Layer 3, buried top: Global GND, except at TZA3005, where it carries the TTL lines
Layer 4, buried bottom: Global GND
Layer 2, bottom: Signal.
A global GND is used, mostly at layer 3 and 4
Under all high speed ICs the GND layers are connected with multiple as-large-as-possible vias, to reduce
parasitic inductance between the GND planes.
The supply lines of the board are configured as star from connector to ICs/blocks.
The decoupling of all ICs/blocks is done with a two stage pi network: from the connector an individual line goes to
the first pi network near the IC/block. Then all the voltage domains are individually decoupled by a pi filter. This
filter is placed near the voltage domain pin. The last capacitor is placed as close as possible to the IC/block.
Fig.5 General setup of power supply decoupling network: From the global domain a pi filter provides the voltage for the local
voltage domains. Capacitor C2 is placed as close as possible to the IC to reduce parasitic inductance.
+
IC
C1
C2
L1
V
CC(globa)
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