參數(shù)資料
型號: TZA1048TH
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: 4-channel BTL driver for CD/DVD drives
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝: PLASTIC, HEAT SINK, SOP-28
文件頁數(shù): 6/17頁
文件大?。?/td> 104K
代理商: TZA1048TH
2004 Mar 09
6
Philips Semiconductors
Product specification
4-channel BTL driver for CD/DVD drives
TZA1048
7
FUNCTIONAL DESCRIPTION
7.1
General notes
1.
The integral thermal shut-down circuit mutes the
output current when the chip temperature reaches
175
°
C (typical). The hysteresis is set to 25
°
C
(typical), so the circuit will restart when the chip
temperature falls to 150
°
C (typical).
Mute mode is activated when the voltage at pin MUTE
is below 0.5 V, and deactivated when the voltage at
pin MUTE is above 1.2 V. In mute mode, both positive
and negative output terminals will be at
high-impedance state. However, the 3.3 V and 1.8 V
outputs are not affected.
It is recommended that a 220
μ
F decoupling capacitor
is connected between pins V
CC
and pin GND and
physically located as close as possible to these supply
pins.
The positive outputs of the focus, radial and sled driver
channels are in phase with their respective input
signals. The positive output of the spindle driver
channel is in phase with the input signal on
pin MOTIN1.
The values of the resistors connected to each input
channel must be equal to, or larger than, 4.7 k
to
ensure that the gain of each input stage is less than, or
equal to 1.
The GND pins are internally connected to heat
dissipation fins within the package. You must ensure
that these pins are connected to an external ground.
The 1.65 V bias voltage output from pin VBIASOUT is
derived from the internal 3.3 V generator/regulator,
and will be affected by any variation in the 3.3 V
generator/regulator voltage.
2.
3.
4.
5.
6.
7.
TZA1048TH
V
CC
VOUT3.3
RADOUTN
VFBIN3.3
FOCOUTP
VOUT1.8
GND
VFBIN1.8
FOCOUTN
MUTE
RADOUTP
RADIN
V
CC
FOCIN
V
CC
SLIN
SLOUTP
VBIASIN
SLOUTN
GND
GND
VBIASOUT
MOTOUTP
MOTBIAS
MOTOUTN
MOTIN1
V
CC
MOTIN2
mce471
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
Fig.2 Pin configuration.
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