參數(shù)資料
型號(hào)： TXN132204015AX2
廠商： INTEL CORP
元件分類： 光收發(fā)
英文描述： FIBER OPTIC TRANSCEIVER, 10000Mbps(Tx), 10000Mbps(Rx), PANEL MOUNT, THROUGH HOLE MOUNT, FC/UPC CONNECTOR
封裝： ROHS COMPLIANT PACKAGE
文件頁(yè)數(shù)： 26/52頁(yè)
文件大?。?/td> 1394K
代理商： TXN132204015AX2
Intel TXN13220/1/4/5/7/8 SFF 10 Gbps Optical Transceiver
Intel TXN13220/1/4/5/7/8 SFF 10 Gbps Optical Transceiver
Datasheet
26-Oct-2006
32
Order Number: 273807004
3.4
Data Input/Output Configuration
The TXN13220/1/4/5/7/8 Transceiver product line of transceivers fully compliant with
OIF standards for LVDS I/O data format.
Bit ordering is compliant with SONET requirements, whereby the most-significant bit is
transmitted first. SONET bit ordering is maintained for all data rates.
Table 37 lists the I/O configuration.
Table 37. Data Input/Output Configuration
Pin Name
In/
Out
Description
Logic
TxDin0P(N), …,
TxDin15P(N)
In
Transmitter (1/16 line bit rate) data input, differential
pairs.
LVDS, internally 100
Ω
terminated
TxPICLKP(N)
In
Transmitter (1/16 line bit rate) input clock, differential
pair, aligned with input data
LVDS, internally 100
Ω
terminated
TxREFCLKP(N)
In
Transmitter reference clock input, differential pair.
Selectable between 1/64 line bit rate and 1/16 line bit
rate MHz using TxREFSEL
LVPECL, AC Coupled
TxPCLKP(N)
Out
Transmitter (1/16 line bit rate) reference clock output,
differential pair
LVDS
RxDout0P(N), …,
RxDout15P(N)
Out
Receiver (1/16 line bit rate) data output, differential
pairs
LVDS
RxREFCLKP(N)
In
Receiver reference clock input, differential pair.
Selectable between 1/64 line bit rate and 1/16 line bit
rate MHz using RxREFSEL
LVPECL, AC Coupled
RxPOCLKP(N)
Out
Receiver (1/16 line bit rate) MHz clock output,
differential pairs, aligned with output data
LVDS
RxMCLKP(N)
Out
Demultiplexer monitor clock output. Selectable
between 1/64 line bit rate and 1/16 line bit rate MHz
by using RxMCLKSEL
LVDS
TxMCLKP(N)
Out
Multiplexer monitor clock output: 1/64 line bit rate
MHz
LVDS
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