參數(shù)資料
型號(hào)： TVP6000CPFP
廠商： Texas Instruments, Inc.
英文描述： NTSC/PAL Digital Video Encoder
中文描述： NTSC / PAL數(shù)字視頻編碼器
文件頁(yè)數(shù)： 23/57頁(yè)
文件大?。?/td> 268K
代理商： TVP6000CPFP
2–11
10
μ
S
(7 Cycles)
13.9
μ
S
27.4
μ
S
Transition
Time: 200 ns
2 Null Characters
59.67
μ
S
Figure 2–11. NTSC Square Pixel Rate Closed Caption Line
10.2
μ
S
(7 Cycles)
13.9
μ
S
27.5
μ
S
Transition
Time: 200 ns
2 Null Characters
61.2
μ
S
Figure 2–12. PAL Square Pixel Rate Closed Caption Line
Clock Generation
When the CDIR pin is tied low, the TVP6000 generates the clock from the crystal connected between XTAL1
and XTAL2. Optionally, an oscillator connected to XTAL1 can also be used. The clock is used internally and
is also properly buffered and output at the LLC pin. The clock qualifying reference signal, CREF, is also an
output in this mode.
2.7
When CDIR is tied high, the LLC and CREF pins are inputs. The TVP6000 receives the clock signal from
the LLC pin and the clock qualifying reference signal from the CREF pin.
2.8
Analog Output
The TVP6000 supports simultaneous composite and S-video outputs. Additionally, the DACs may be
independently turned off via software to minimize power dissipation.
The output DACs are current sources and are optimal for driving a 37.5-
load with double 75-
termination.
A 264-
full-scale adjust resistor must be connected between the FSADJ pin and ground.
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