參數(shù)資料
型號(hào)： TVP5022
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù)： 24/91頁(yè)
文件大?。?/td> 411K
代理商： TVP5022
2–14
2.6.1
I2C Host Port Select
The I2C standard consists of two signals, serial input/output data (VC1) line and input/output clock line
(VC0), that carry information between the devices connected to the bus. A third signal (VC3) is used for slave
address selection. Although the I2C system can be multimastered, the TVP5022 will function as a slave
device only.
Both SDA and SCL are bidirectional lines that connect to a positive supply voltage via a pullup resistor. When
the bus is free, both lines are high.
The slave address select terminal (VC3) enables the use of two TVP5022 devices tied to the same I2C bus.
Table 2–3 summarizes the terminal functions of the I2C mode host interface.
Table 2–3. I2C Host Port Terminal Description
SIGNAL
TYPE
DESCRIPTION
VC3 (I2CA)
I
Slave address selection
VC0 (SCL)
I/O (OD)
Input/output clock line
VC1 (SDA)
I/O (OD)
Input/output data line
NOTE: OD = Open drain
1–7
Address
8
RW
9
ACK
1–7
Data
8
Data
9
ACK
1–7
Data
8
Data
9
ACK
P
S
VC1
(SDA)
VC0
(SCL)
Start Condition
VC0
(SCL)
Stop
12C Data Transfer
Figure 2–20. I2C Data Transfer Example
Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent
on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of
the clock. The high or low state of the data line can only change with the clock signal on the SCL line being
low.
When transferring multiple bytes during one read or write operation, the internal subaddress is
not automatically incremented.
A high to low transition on the SDA line while the SCL is high indicates a start condition.
A low to high transition on the SDA line while the SCL is high indicates a stop condition
Acknowledge is signalled by SDA low during the ninth SCL high.
Not-acknowledge is signalled by SDA high during the ninth SCL high.
Every byte placed on the SDA line must be 8 bits long. The number of bytes that can be transferred is
unrestricted. An acknowledge bit follows each byte. If the slave can not receive another complete byte of
data until it has performed another function, it holds the clock line (SCL) low. An SCL low forces the master
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