參數(shù)資料
型號： TUA6036-T
廠商： INFINEON TECHNOLOGIES AG
元件分類： 調(diào)諧器
英文描述： 3-BAND, VIDEO TUNER, PDSO38
封裝： TSSOP-38
文件頁數(shù)： 19/65頁
文件大?。?/td> 1391K
代理商： TUA6036-T
Specification
26
V 2.51, 2006-01-11
TUA6034, TUA6036
TAIFUN
Functional Description
The software controlled ports P0 to P4 are general purpose open-collector outputs. The
test bits T2, T1, T0 =1, 0, 0 switch the test signals f
div (divided input signal) and fref (i.e
.4 MHz / 64) to P0 and P1 respectively.
The lock detector resets the lock flag FL if the width of the charge pump current pulses
is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL = 1, the
maximum deviation of the input frequency from the programmed frequency is given by
f = ± I
P (KVCO / fXTAL) (C1+C2) / (C1C2)
where I
P is the charge pump current, KVCO the VCO gain, fXtal the crystal oscillator
frequency and C
1, C2 the capacitances in the loop filter (see Chapter 3 on page 28). As
the charge pump pulses at i.e. 62.5 kHz (= f
ref), it takes a maximum of 16 s for FL to be
reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns
for eight consecutive f
ref periods. Therefore it takes between 128 and 144 s for FL to be
set after the loop regains lock.
2.4.3
AGC
The wide band AGC stage detects the level of the IF output signal and generates an
AGC voltage for gain control of the tuners input transistors. The AGC take-over and the
time constant are selectable by the I
2C bus.
2.4.4
I
2C-Bus Interface
Data is exchanged between the processor and the PLL via the I
2C bus. The clock is
generated by the processor (input SCL). Pin SDA functions as an input or output
depending on the direction of the data (open collector, external pull-up resistor). Both
inputs have a hysteresis and a low-pass characteristic, which enhance the noise
immunity of the I
2C bus.
The data from the processor pass through an I
2C bus controller. Depending on their
function the data are subsequently stored in registers. If the bus is free, both lines will be
in the marking state (SDA, SCL are high). Each telegram begins with the start condition
and ends with the stop condition. Start condition: SDA goes low, while SCL remains high.
Stop condition: SDA goes high while SCL remains high. All further information transfer
takes place during SCL = low, and the data is forwarded to the control logic on the
positive clock edge.
The table ’Bit Allocation’ (see Table 8 Bit Allocation Read/Write on page 50) should be
referred to for the following description. All telegrams are transmitted byte-by-byte,
followed by a ninth clock pulse, during which the control logic returns the SDA line to low
相關(guān)PDF資料
PDF描述
TUA6039F-2 3-BAND, VIDEO TUNER, QCC48
TUA6037F 3-BAND, VIDEO TUNER, QCC48
TUA6039 3-BAND, VIDEO TUNER, QCC48
TUA6039-2 3-BAND, VIDEO TUNER, QCC48
TUA6037 3-BAND, VIDEO TUNER, QCC48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TUA6036TXT 制造商:Infineon Technologies AG 功能描述:Tuners PAL/NTSC 863.25MHz 38-Pin TSSOP
TUA6037 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3 Band Digital / Hybrid Tuner IC with integrated IF AGC amplifier
TUA6037F 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3 Band Digital / Hybrid Tuner IC with integrated IF AGC amplifier
TUA6037FXT 制造商:Infineon Technologies AG 功能描述:Tuners PAL/NTSC 863.25MHz 48-Pin VQFN EP
TUA6039 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3 Band Digital / Hybrid Tuner IC with integrated IF AGC amplifier
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