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參數(shù)資料
| 型號(hào)： | TUA6024-K |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | 2-BAND, VIDEO TUNER, PDSO28 |
| 封裝： | 1 MM HEIGHT, PLASTIC, TSSOP-28 |
| 文件頁(yè)數(shù)： | 22/34頁(yè) |
| 文件大?。?/td> | 631K |
| 代理商： | TUA6024-K |
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Reference
5 - 10
TUA6024
Wireless Components
Specification, December 1999
5.2 Programming
Table 5-4 Bit Allocation Read / Write
Byte
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
Ack
Remark
s
Write Data
Address Byte
11
00
0MA1
MA0
0
A
Progr. Divider
Byte 1
0N14
N13
N12
N11
N10
N9
N8
A
Progr. Divider
Byte 2
N7
N6
N5
N4
N3
N2
N1
N0
A
Control Byte
1CP
T1
T0
FP
RSA
RSB
OS
A
Bandswitch
Byte
xx
xP-
HIGH
PMID
1).
PLOW
1.)
A
TUA
6024-K
Bandswitch
Byte
xx
P-
HIGH
x
PMID
1.)
PLOW
1.)
A
TUA
6024-S
Read Data
Address Byte
11
00
0MA1
MA0
1
A
Status Byte
POR
FL
xx
A
1). In a tuner PLOW and PMID are interchangeable. Both bits switch the IC into LOW/MID (VHF) mode.
Table 5-5 Description of symbols
Symbol
Description
MA0, MA1
Address selection bits (see Table 5-6 Address selection on page 11)
N14 to N0
programmable divider bits:
N = 214 x N14 + 213 x N13 + ..... + 23 x N3 + 22 x N2 + 21 x N1 + N0
CP
charge pump current:
bit = 0: charge pump current = 50 A
bit = 1: charge pump current = 220A
T1, T0
test bits (see Table 5-7 Test modes on page 11)
FP
reserved for future purposes, actually ignored, default: 1
RSA, RSB
reference divider bits (see Table 5-8 Reference divider ratio on page 11)
OS
tuning amplifier control bit:
bit = 0: enable VT
bit = 1: disable VT
PLOW, PMID, PHIGH
NPN ports control bits:
bit = 0: NPN open-collector output is inactive
bit = 1: NPN open-collector output is active
FL
PLL lock flag
bit = 1: loop is locked
POR
Power-on reset flag
flag is set at power-on and reset at the end of READ operation
x
don‘t care
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