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參數(shù)資料
| 型號(hào)： | TTS3816B4E-6D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 2M x 16Bit x 4 Banks synchronous DRAM |
| 中文描述： | 200萬(wàn)× 16 × 4銀行同步DRAM |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 274K |
| 代理商： | TTS3816B4E-6D |
M
.tec
T
T
S3816B4E
Revision_1.1
3
TwinMOS Technologies Inc.
Sep. 2000
PIN FUNCTION DESCRIPTION
Pin Name
A0~ A11
Address
Function
Description
Multiplexed pins for row and column address Row address: A0 ~ A11.
Column address: A0 ~ A8.
BS0, BS1
Bank
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
DQ0 ~DQ15
Data Input / Output
Multiplexed pins for data output and input.
/CS
Chip Select
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
/RAS
Row Address Strobe
Command input. When sampled at the rising edge of the clock, /RAS,
/CAS and /WE define the operation to be executed.
/CAS
Column Address Strobe
Referred to /RAS
/WE
Write Enable
Referred to /RAS
UDQM/LDQM
Input /output mask
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
System clock used to sample inputs on the rising edge of clock.
CLK
Clock Input
CKE
Clock Enable
CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self Refresh mode is entered.
Vcc
Power (+3.3 V)
Power for input buffers and logic circuit inside DRAM.
Vss
Ground
Ground for input buffers and logic circuit inside DRAM.
Vcc
Q Power (+ 3.3 V) for I/O
buffer
Separated power from
VCC
, used for output buffers to improve noise.
Vss
Q Ground for I/O buffer
Separated ground from
VSS
, used for output buffers to improve noise.
NC
No Connection
No connection
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| TTS3816B4E-6E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M x 16Bit x 4 Banks synchronous DRAM |
| TTS3816B4E-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M x 16Bit x 4 Banks synchronous DRAM |
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