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參數(shù)資料
| 型號： | TSW5070FNTR |
| 廠商： | 意法半導體 |
| 元件分類： | Codec |
| 英文描述： | PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION |
| 中文描述： | 可編程解碼器/濾鏡組合第二代 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 284K |
| 代理商： | TSW5070FNTR |
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struction;and bit0 isnot used.To shiftcontroldata
into COMBO IIG, CCLK must be pulsed high 8
timeswhileCSis low.Dataon the CI or CI/Oinput
is shiftedinto the serial input registeron the falling
edge of each CCLK pulse. After all data is shifted
in, the contents of the input shift register are de-
coded, and may indicatethat a 2nd byte of control
data willfollow. Thissecondbyte mayeitherbe de-
finedby asecondbyte-wideCSpulseor mayfollow
thefirstcontinuously,i.e. it isnotmandatoryfor CS
to return high in betweenthe first and secondcon-
trolbytes.Onthefallingedgeof the8
th
CCLKclock
pulse in the2ndcontrolbytethe datais loadedinto
theappropriateprogrammableregister.CSmayre-
mainlow continuouslywhen programmingsucces-
Table 1:
ProgrammableRegisterInstructions
siveregisters,ifdesired.HoweverCSshouldbe set
high when no data transfersare in progress.
ToreadbackinterfaceLatchdataor statusinforma-
tionfrom COMBOIIG,the first byteof theappropri-
ateinstructionisstrobedinduringthefirstCSpulse,
asdefinedintable1.CSmust thenbetakenlow for
a further 8 CCLK cycles, during which the data is
shiftedontothe CO or CI/O pinon therisingedges
of CCLK.When CS is high the CO or CI/Opin is in
thehigh-impedanceTRI-STATE,enablingtheCI/O
pins of many devices to be multiplexed together.
Thus, to summarize, 2-byte READ and WRITE in-
structionsmay use eithertwo8-bit wideCS pulses
or a single 16-bit wide CS pulse.
Function
Byte 1
Byte 2
7
6
5
4
3
2
1
0
Single Byte Power–up/down
P
X
X
X
X
X
0
X
None
Write Control Register
Read–back Control Register
P
P
0
0
0
0
0
0
0
0
0
1
1
1
X
X
See Table 2
See Table 2
Write Latch Direction Register (LDR)
Read Latch Direction Register
P
P
0
0
0
0
1
1
0
0
0
1
1
1
X
X
See Table 4
See Table 4
Write Latch Content Register (ILR)
Read Latch Content Register
P
P
0
0
0
0
0
0
1
1
0
1
1
1
X
X
See Table 5
See Table 5
Write Transmit Time–slot/port
Read–back Transmit Time–slot/port
P
P
1
1
0
0
1
1
0
0
0
1
1
1
X
X
See Table 6
See Table 6
Write Receive Time–slot/port
Read–back Receive Time–slot/port
P
P
1
1
0
0
0
0
1
1
0
1
1
1
X
X
See Table 6
See Table 6
Write Transmit GainRegister
Read Transmit GainRegister
P
P
0
0
1
1
0
0
1
1
0
1
1
1
X
X
See Table 7
See Table 7
Write Receive GainRegister
Read Receive Gain Register
P
P
0
0
1
1
0
0
0
0
0
1
1
1
X
X
See Table 8
See Table 8
Write Hybrid Balance Register
≠
1
Read Hybrid BalanceRegister
≠
1
P
P
0
0
1
1
1
1
0
0
0
1
1
1
X
X
See Table 9
See Table 9
Write Hybrid Balance Register
≠
2
Read Hybrid BalanceRegister
≠
2
P
P
0
0
1
1
1
1
1
1
0
1
1
1
X
X
See Table 10
See Table 10
Write Hybrid Balance Register
≠
3
Read Hybrid BalanceRegister
≠
3
P
P
1
1
0
0
0
0
0
0
0
1
1
1
X
X
PROGRAMMABLE FUNCTIONS
POWER-UP/DOWN CONTROL
Following power-on initialization, power-up and
power-down control may be accomplished by
writing any of the control instructions listed in ta-
ble 1 into COMBO IIG with the ”P” bit set to ”0”
for power-up or ”1” for power-down. Normally it is
recommendedthat all programmablefunctionsbe
initially programmed while the device is powered
down. Power state control can then be included
with the last programming instruction or the sepa-
rate single-byte instruction. Any of the program-
mable registers may also be modified while the
device is powered-up or down be setting the ”P”
bit as indicated. When the power up or down con-
trol is entered as a single byte instruction, bit one
(1) must be set to a 0.
When a power-up command is given, all de-acti-
vated circuits are activated, but the TRI-STATE
PCM output(s), D
X
0 (and D
X
1), will remain in the
high impedance state until the second FS
X
pulse
after power-up.
Notes:
1. Bit 7 of bytes 1 and 2 is always the first bit clocked into or out of the CI, CO or CI/CO pin.
2. ”P” is the power-up/down control bit, see ”Power-up” section (”0” = Power Up ”1” = Power Down).
TS5070 - TS5071
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