- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373744 > TSPC106AVG (Atmel Corp.) PCI Bus Bridge Memory Controller 66-83 MHz PDF資料下載
參數(shù)資料
| 型號： | TSPC106AVG |
| 廠商： | Atmel Corp. |
| 英文描述： | PCI Bus Bridge Memory Controller 66-83 MHz |
| 中文描述： | PCI總線橋66-83 MHz的內(nèi)存控制器 |
| 文件頁數(shù)： | 14/41頁 |
| 文件大?。?/td> | 581K |
| 代理商： | TSPC106AVG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
14
TSPC106A
2102C–HIREL–01/05
Multiple Processor
Signals
When a system implementation uses more than one 60x processor, nine of the internal
L2 cache controller signals change their functions.
Note that in a multi-processor system, with the exception of the bus grant, bus request
and data bus grant signals, all of the 60x processor interface signals are shared by all
60x processors.
Table 5.
Multiple Processor Signals
Signal
Signal Name
Number of
Pins
I/O
Signal Description
BG1
DIRTY_OUT
Bus grant 1
1
O
Indicates that processor 1 may, with the proper qualification, begin a
60x bus transaction and assume mastership of the address bus.
BG2
TWE
Bus grant 2
1
O
Indicates that processor 2 may, with the proper qualification, begin a
60x bus transaction and assume mastership of the address bus.
BG3
DCS
Bus grant 3
1
O
Indicates that processor 3 may, with the proper qualification, begin a
60x bus transaction and assume mastership of the address bus.
BR1
DIRTY_IN
Bus request 1
1
I
Indicates that processor 1 requires mastership of the 60x bus for a
transaction.
BR2
TV
Bus request 2
1
I
Indicates that processor 2 requires mastership of the 60x bus for a
transaction.
BR3
BA0
Bus request 3
1
I
Indicates that processor 3 requires mastership of the 60x bus for a
transaction.
DBG1
TOE
Data bus grant 1
1
O
Indicates that processor 1 may, with the proper qualification, assume
mastership of the 60x data bus.
DBG2
DWE0
Data bus grant 2
1
O
Indicates that processor 2 may, with the proper qualification, assume
mastership of the 60x data bus.
DBG3
DWE1
Data bus grant 3
1
O
Indicates that processor 3 may, with the proper qualification, assume
mastership of the 60x data bus.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSPC106AMGS | PCI Bus Bridge Memory Controller 66-83 MHz |
| TSPC860 | Integrated Communication Processor |
| TSPC860XRMZPU66D | Integrated Communication Processor |
| TSPC860XRMZQU66D | Integrated Communication Processor |
| TSPC860XRVZPU66D | Integrated Communication Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSPC106AVG66CE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AVG66CG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AVG83CE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AVG83CG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| TSPC106AVGS | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bus Bridge Memory Controller 66-83 MHz |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。