參數(shù)資料
型號(hào)： TSP5071N
廠商： 意法半導(dǎo)體
元件分類(lèi)： Codec
英文描述： PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION
中文描述： 可編程解碼器/濾鏡組合第二代
文件頁(yè)數(shù)： 18/32頁(yè)
文件大小： 284K
代理商： TSP5071N
TIMING SPECIFICATIONS
Unlessotherwisenoted,limitsinBOLDcharactersare
guaranteedforV
CC
=+ 5V
±
5 %;V
SS
= -5V
±
5 %
.
T
A
= -40
°
Cto 85
°
C bycorrelationwith100 %elec-
trical testing at T
A
= 25
°
C. All other limits are as-
sured by correlation with other production tests
and/orproduct design and characterization. All sig-
nals referenced to GND. Typicals specified at
V
CC
= + 5 V, V
SS
= -5 V, T
A
= 25
°
C. All timingpa-
rametersaremeasuredatV
OH
=2.0VandV
OL
=0.7V.
See Definitions and Timing Conventions section
for test methods information.
ELECTRICALOPERATING CHARACTERISTICS
(continued)
POWERDISSIPATION
Symbol
ICC0
Parameter
Min.
Typ.
0.3
Max.
1.5
Unit
mA
Power Down Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)
Interface Latches set as Outputs with no load
All over Inputs active, Power Amp Disabled
Power Down Current (as above)
Power Up Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)
No Load on Power Amp
Interface Latches set as Outputs with no Load
Power Up Current (as above)
Power Down Current with Power Amp Enabled
Power Down Current with Power Amp Enabled
-ISS0
ICC1
0.1
0.3
mA
7
7
2
2
11
11
4
4
mA
mA
mA
mA
-ISS1
ICC2
-ISS2
MASTER CLOCKTIMING
Symbol
Parameter
Min.
Typ.
Max.
Unit
f
MCLK
Frequency of MCLK
(selection of frequency is programmable, see table 2)
512
1.536
1.544
2.048
4.096
kHz
MHz
MHz
MHz
MHz
t
WMH
Period ofMCLK High (measured from V
IH
to V
IH
, see note 1)
80
ns
t
WML
Period ofMCLK Low (measured from V
IL
to V
IL
, see note 1 )
80
ns
t
RM
Rise Time of MCLK (measured from V
IL
or V
IH
)
30
ns
t
FM
Fall Time of MCLK (measured from V
IH
to V
IL
)
30
t
HBM
Hold Time, BCLK Low to MCLK High (TS5070 only)
50
ns
t
WFL
Period ofFS
X
or FS
R
Low (Measured from V
IL
to V
IL
)
1
(*)
(*) MCLK period
TS5070 - TS5071
18/32
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