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參數(shù)資料
| 型號(hào)： | TSLW201R |
| 廠商： | TAOS Inc. |
| 英文描述： | 64 x 1 LINEAR SENSOR ARRAY |
| 中文描述： | 64 × 1線性傳感器陣列 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大小： | 116K |
| 代理商： | TSLW201R |
TSLW201R
64 1 LINEAR SENSOR ARRAY
TAOS047B – JANUARY 2003
2
Copyright 2003, TAOS Inc.
The LUMENOLOGY Company
www.taosinc.com
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
AO
3
Analog output.
CLK
2
Clock. The clock controls charge transfer, pixel output, and reset.
GND
5, 6, 7, 8
Ground (substrate). All voltages are referenced to the substrate.
SI
1
Serial input. SI defines the start of the data-out sequence.
V
DD
4
Supply voltage. Supply voltage for both analog and digital circuits.
Detailed Description
The sensor consists of 64 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration
time. The integration time is the interval between two consecutive output periods.
The output and reset of the integrators is controlled by a 64-bit shift register and reset logic. An output cycle is
initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)
. As the SI pulse
is clocked through the 64-bit shift register, the charge on the sampling capacitor of each pixel is sequentially
connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes
low, the pixel integrator is reset. On the 65th clock rising edge, the SI pulse is clocked out of the shift register
and the output assumes a high-impedance state. Note that this 65th clock pulse is required to terminate the
output of the 64th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented
on the 66th clock pulse, thereby initiating another pixel output cycle.
The voltage developed at analog output (AO) is given by:
V
out
= V
drk
+ (R
e
) (E
e
) (t
int
)
where:
V
out
V
drk
R
e
E
e
t
int
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(
μ
J/cm
2
)
is the incident irradiance in
μ
W/cm
2
is integration time in seconds
AO is driven by a source follower that requires an external pulldown resistor (330 ohms typ.). The source
follower configuration permits an analog wired OR hookup of multiple devices. When the device is not in the
output phase AO is in a high impedance state. The output is nominally 0 volts for no light and 2 volts for a nominal
white level output, with a nominal full-scale (saturation) voltage of 2.5V.
A 0.1
μ
F bypass capacitor should be connected between V
DD
and ground as close as possible to the device.
For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.
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