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參數(shù)資料
| 型號(hào)： | TSL3301 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 102 】 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOGTODIGITAL CONVERTER |
| 中文描述： | 102】1的模擬線性光學(xué)傳感器陣列數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大?。?/td> | 153K |
| 代理商： | TSL3301 |
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TSL3301
102
×
1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOGTODIGITAL CONVERTER
TAOS026 – FEBRUARY 2001
10
www.taosinc.com
Copyright 2001, TAOS Inc.
Light-to-Digital Transfer Characteristics at V
DD
= 5 V, T
J
= 25
°
C,
λ
p
= 660 nm, t
int
= 250
μ
s (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A-to-D converter resolution
8
Bits
Full scale reference
Full-scale reference
Gain register = 00000b
3.6
nJ/cm
2
Gain register = 11111b
1.24
Full-scale reference temperature sensitivity
For converter only, does not include
photodiode characteristics
±
150
ppm/
°
C
Average dark level offset
Average dark-level offset
Gain register = 00000b
Offset register = 00000000b
0
7
30
LSB
Gain register = 11111b
20
Dark signal nonuniformity (DSNU)
Gain register = 00000b, see Note 1
5
10
LSB
Gain register = 11111b, see Note 1
14
Average white level output
Offset register =
00000000b
Gain register = 00000b
Ee = 11.3
μ
W/cm
2
160
200
240
LSB
Gain register = 11111b
Ee = 3.77
μ
W/cm
2
Ee = 11.3
μ
W/cm
2
, See Notes 2 and 3
200
Photo-response non-uniformity (PRNU)
±
4%
±
128
0.5
±
5%
Programmable offset steps
Programmable offset step size
Gain register = 00000b
LSB
Gain register = 11111b
1.5
Dark-level change with temperature
0
°
C < T
J
< 70
°
C
2
LSB
Differential nonlinearity
±
0.5
±
1
0.5
1.5
LSB
Integral nonlinearity
LSB
Dark level noise
Gain register = 00000b
Gain register = 11111b
LSB
NOTES:
1. DSNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is not
illuminated.
2. PRNU does not include DSNU.
3. PRNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is uniformly
illuminated at nominal white level (typical average output level = 200).
Timing Requirements over recommended operating range (unless otherwise noted) (Figure 2)
MIN
NOM
MAX
UNIT
f
max
t
w(CLKH)
t
w(CLKL)
t
su
t
h
Maximum clock frequency
10
MHz
Clock high pulse duration
30
ns
Clock low pulse duration
30
ns
Input setup time
20
ns
Input hold time
20
ns
Switching Characteristics over recommended operating range (unless otherwise noted) (Figure 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX
UNIT
ns
t
r
t
f
t
d
C
i
Rise time, output
C
L
= 20 pF
Fall time, output
10
ns
Delay from clock edge to data-out stable
20
ns
Input pin capacitance
10
pF
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