參數(shù)資料
型號(hào): TSEV8388BF
廠商: Atmel Corp.
元件分類: ADC
英文描述: ADC 8-bit 1 GSPS
中文描述: ADC的8位1 GSPS的
文件頁(yè)數(shù): 5/57頁(yè)
文件大?。?/td> 1276K
代理商: TSEV8388BF
5
TS8388B
2144C–BDC–04/03
Positive supply current
Analog
Digital
I
CC
I
PLUSD
1, 2
6
1, 2
6
385
395
115
120
445
445
145
145
mA
mA
mA
mA
Negative supply voltage
V
EE
1, 2, 6
-5.3
-5
-4.7
V
Negative supply current
Analog
Digital
AI
EE
DI
EE
1, 2
6
1, 2
6
165
170
135
145
200
200
180
180
mA
mA
mA
mA
Nominal power dissipation
PD
1, 2
6
3.4
3.6
4.1
4.3
W
W
Power supply rejection ratio
PSRR
4
0.5
2
mW
Resolution
8
bits
(2)
Analog Inputs
Full Scale Input Voltage range (differential mode)
(0V common mode voltage)
V
IN
V
INB
4
-125
-125
125
125
mV
mV
Full Scale Input Voltage range (single-ended input
option) (See Application Notes)
V
IN
V
INB
4
-250
0
250
mV
mV
Analog input capacitance
C
IN
4
3
3.5
pF
Input bias current
I
IN
4
10
20
μA
Input Resistance
R
IN
4
0.5
1
M
Full Power input Bandwidth (-3dB)
CBGA68 package
CQFP68 package
FPBW
4
4
1.8
1.5
GHz
GHz
Small signal input Bandwidth (10% full scale)
SSBW
4
1.5
1.7
GHz
Clock Inputs
Logic compatibility for clock inputs
(See Application Notes)
ECL or specified clock input
power level in dBm
(10)
ECL Clock inputs voltages (V
CLK
or V
CLKB
):
4
Logic “0” voltage
V
IL
-1.5
V
Logic “1” voltage
V
IH
-1.1
V
Logic “0” current
I
IL
5
50
μA
Logic “1” current
I
IH
5
50
μA
Clock input power level into 50
termination
dBm into 50
Clock input power level
4
-2
4
10
dBm
Clock input capacitance
C
CLK
4
3
3.5
pF
Table 3.
Electrical Specifications (Continued)
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
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