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參數(shù)資料
| 型號(hào)： | TSCD114DCU6 |
| 廠商： | Taiwan Semiconductor Co., Ltd. |
| 英文描述： | NPN Digital Transistor |
| 中文描述： | npn型數(shù)字晶體管 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 136K |
| 代理商： | TSCD114DCU6 |
TSCD114D
1-4
2003/12 rev. A
TSCD114D
NPN Digital Transistor
Vcc = 50V
Vin = - 6V ~ +40V
Io = 70mA(max.)
Features
Build-in bias resistor enable the configuration of an
inverter circuit without connecting external input
resistors (see equivalent circuit)
The bias resistors consist of thin-film resistors with
complete isolation to allow negative biasing of the
input. The also have the advantage of almost
completely eliminating parasitic effects.
Only the on/off conditions need to be set for operation,
making device design easy.
Two TSC114D chips in a SOT-363 package
Transistor elements are independent, eliminating
interference
Complements the TSAD114D
Ordering Information
Part No.
Packing
Package
TSCD114DCU6
Note: the build-in resistor value type, option as
No.
Re (K
)
TR 1
TR 2
Tape & Reel
SOT-363
R (K
)
47
47
Marking
7D
10
10
Equivalent Circuit
Absolute Maximum Rating
(Ta = 25
o
C
unless otherwise noted)
Parameter
Symbol
Limit
Unit
Supply Voltage
Vcc
50
V
Input Voltage
Vin
- 6 ~ +40
V
DC
70
Output Current
Pulse
Io
100
mA
Power Dissipation (note)
P
D
200
mW
Operating Junction Temperature
T
J
+150
o
C
Operating Junction and Storage Temperature Range
Note: 1. Single pulse, Pw = 300uS, Duty <= 2%
2. 150mW per element must not be exceeded.
T
STG
- 55 to +150
o
C
Pin assignment:
1. TR1 Gnd (Emitter)
2. TR1 Input (Base)
3. TR2 Output (Collector)
4. TR2 Gnd (Emitter)
5. TR2 Input (Base)
6. TR1 Output (Collector)
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