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      參數(shù)資料
      型號(hào)： TSC87C52-L16CAB
      英文描述： CMOS 0 to 33 MHz Programmable 8朾it Microcontroller
      中文描述： 的CMOS 0至33 MHz的可編程微控制器8朾它
      文件頁(yè)數(shù)： 7/24頁(yè)
      文件大小： 273K
      代理商： TSC87C52-L16CAB
      TSC87C52
      7
      MATRA MHS
      Rev. C – 10 Sept 1997
      Preliminary
      While the TSC87C52 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 2 shows the
      status of the port pins during ONCE mode.
      Normal operation is restored when normal reset is applied.
      Table 2 External pin status during ONCE mode
      ALE
      PSEN
      Port 0
      Port 1
      Port 2
      Port 3
      XTAL1/2
      Weak pull–up
      Weak pull–up
      Float
      Weak pull–up
      Weak pull–up
      Weak pull–up
      Active
      ALE Disabling
      The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data
      memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE
      signal should be disabled by setting AO bit.
      The AO bit is located in MSCON at bit location 0 (see Table 3). As soon as AO is set, ALE is no longer output but
      remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly
      pulled high.
      Table 3 MSCON – Miscellaneous Control Register (8Eh)
      7
      6
      5
      4
      3
      2
      1
      0
      –
      –
      –
      –
      –
      –
      –
      AO
      Symbol
      Description
      –
      Reserved
      Do not write 1 in these bits.
      AO
      ALE Output bit
      Set to disable ALE operation during internal fetches.
      Clear to restore ALE operation during internal fetches.
      The reset value of MSCON is XXXX XXX0b.
      UART
      The UART in the TSC87C52 operates identically to the UART in the 80C51 but includes the following enhancement.
      For a complete understanding of the TSC87C52 UART please refer to the description in the 80C51 Hardware
      Description Guide.
      Framing Error Detection
      Framing error detection allows the serial port to check for missing stop bits in the communication in mode 1, 2 or 3.
      A missing stop bit can be caused for example by noise on the serial lines or transmission by two CPUs simultaneously.
      If a stop bit is missing a Framing Error bit (FE) is set. The FE bit can be checked in software after each reception to
      detect communication errors. Once set, the FE bit must be cleared in software. A valid stop bit will not clear FE.
      The FE bit is located in SCON at bit location 7. It shares the same bit location as SM0 (see Table 4). The new control
      bit SMOD0 in PCON (see Table 1) determines whether the SM0 or FE bit is accessed (see Figure 3), so whether the
      framing error detection is enabled or not. If SMOD0 is set then SCON.7 functions as FE, if SMOD0 is cleared then
      SCON.7 functions as SM0. Once set, the FE bit must be cleared by software. A valid stop bit will not clear FE. When
      UART is in mode 1 (8–bit mode), RI flag is set during stop bit whether or not framing error is enabled (see Figure 4).
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