27
AT/TSC8x251G2D
4135F–8051–11/06
Logical AND(1)ANL <dest>, <src>dest opnd
← dest opnd Λ src opnd
Logical OR(1)ORL <dest>, <src>dest opnd
← dest opnd src opnd
Logical Exclusive OR(1)XRL <dest>, <src>dest opnd
← dest opnd src opnd
Clear(1)CLR A(A)
← 0
Complement(1)CPL A(A)
← (A)
Rotate LeftRL A(A)n+1 ← (A)n, n = 0..6
(A)0 ← (A)7
Rotate Left CarryRLC A(A)n+1 ← (A)n, n = 0..6
(CY)
← (A)7
(A)0 ← (CY)
Rotate RightRR A(A)n-1 ← (A)n, n = 7..1
(A)7 ← (A)0
Rotate Right CarryRRC A(A)n-1 ← (A)n, n = 7..1
(CY)
← (A)0
(A)7 ← (CY)
Mnemonic
<dest>, <src>(1)
Comments
Binary Mode
Source Mode
Bytes
States
Bytes
States
ANL
ORL
XRL
A, Rn
register to ACC
1
2
A, dir8
Direct address (on-chip RAM or SFR) to ACC
2
1(3)
21(3)
A, at Ri
Indirect address to ACC
1
2
3
A, #data
Immediate data to ACC
2
1
2
1
dir8, A
ACC to direct address
2
2(4)
22(4)
dir8, #data
Immediate 8-bit data to direct address
3
3(4)
33(4)
Rmd, Rms
Byte register to byte register
3
2
1
WRjd, WRjs
Word register to word register
3
2
Rm, #data
Immediate 8-bit data to byte register
4
3
2
WRj, #data16
Immediate 16-bit data to word register
5
4
3
Rm, dir8
Direct address (on-chip RAM or SFR) to byte
register
43(3)
32(3)
WRj, dir8
Direct address (on-chip RAM or SFR) to word
register
44
3
Rm, dir16
Direct address (64K) to byte register
5
3(5)
42(5)
WRj, dir16
Direct address (64K) to word register
5
4(6)
43(6)
Rm, at WRj
Indirect address (64K) to byte register
4
3(5)
32(5)
Rm, at DRk
Indirect address (16M) to byte register
4
4(5)
33(5)
CLR
A
Clear ACC
1
CPL
A
Complement ACC
1
RL
A
Rotate ACC left
1
RLC
A
Rotate ACC left through CY
1
RR
A
Rotate ACC right
1
RRC
A
Rotate ACC right through CY
1