參數(shù)資料
型號: TSC2301IPAGRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 68/95頁
文件大?。?/td> 1322K
代理商: TSC2301IPAGRG4
www.ti.com
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Audio Data Converters
The TSC2301 includes a stereo 20-bit audio DAC and a stereo 20-bit audio ADC. The DAC and ADC are both
capable of operating at 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz.
The DAC and ADC must operate at the same sampling rate.
When the ADC or DAC is operating, the part requires an audio MCLK input, which should be synchronous to the
I2S bus clock. The MCLK can be 256/384/512 times the I2S LRCLK rate. An internal PLL takes any of these
possible input clocks and generates a digital clock for use by the internal circuitry of either 44.1 kHz x 512 =
22.5792 MHz (when 44.1 kHz submultiple sample-rates are selected) or 48 kHz x 512 = 24.576 MHz (when 48
kHz submultiple sample-rates are selected). The user is required to set the MCLK bits (Bits[7:6], Reg 00h, Pg 2)
to tell the part the ratio between MCLK and the I2S LRCLK rate (there is no specific phase alignment requirement
between MCLK and BCLK). The user is also required to set the I2SFS bits (Bits[5:2], Reg 00h, Pg 2) to tell the
part what sample rate is in use. When the user is using either 44.1 kHz or 48-kHz sampling rates, and providing
a 512 x Fs MCLK, the internal PLL is powered down, as MCLK can be used directly to clock the internal circuitry.
This reduces power consumption.
If the user wishes to change sampling rates, the data converters (both DACs and ADCs) must be muted, then
powered down. The LRCLK and BCLK rates must then be changed. Next the user must write the appropriate
settings to the MCLK, I2SFS, and I2SFM bits, then power up the data converters. Finally, the data converters
can be unmuted.
Due to the wide supply range over which this part must operate, the audio does not operate on an internal
reference voltage. The common-mode voltage that the single-ended audio signals are referenced to is set by a
divider between the analog supplies and is given by 0.4 x AVDD. The reference voltages used by the audio
codec must be provided as inputs to the part at the Vref+/Vref- pins and are intended to be connected to the
same voltage levels as AVDD and AGND, respectively. Because of this arrangement, the voltages applied to
AVDD, AGND, Vref+, and Vref- should be kept as clean and noise-free as possible.
DAC Digital Volume Control
The DAC digital effects processing block implements a digital volume control that can be set through the SPI
registers. The volume level can be varied from 0 dB to -63.5 dB in 0.5-dB steps independently for each channel.
The user can mute each channel independently by setting the mute bits in the DAC volume control register (Reg
02h, Pg 2). There is a soft-stepping algorithm included in this block, which only changes the actual volume every
20 s, either up or down, until the desired volume is reached. This speed of soft-stepping can be slowed to once
every 40 s through the SSRTE bit (Bit 1, Reg 04h, Pg 2).
Because of this soft-stepping, the host does not know whether the DAC has actually been fully muted or not.
This may be important if the host wishes to mute the DAC before making a significant change, such as changing
sample rates. In order to help with this situation, the part provides a flag back to the host via a read-only SPI
register bit (Bit 0, Reg 04h, Pg 2) that alerts the host when the part has completed the soft-stepping, and the
actual volume has reached the desired volume level.
The part also includes functionality to detect when the user switches on or off the de-emphasis or bass-boost
functions, and to first soft-mute the DAC volume control, then change the operation of the digital effects
processing, then soft-unmute the part. This avoids any possible pop/clicks in the audio output due to
instantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC/ADC.
The circuit begins operation at power-up with the volume control muted, then soft-steps it up to the desired
volume level slowly. At power-down, the logic first soft-steps the volume down to a mute level, then powers down
the circuitry.
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