參數(shù)資料
型號: TSC2200IPWR
英文描述: PDA ANALOG INTERFACE CIRCUIT
中文描述: 掌上電腦模擬接口電路
文件頁數(shù): 33/40頁
文件大?。?/td> 645K
代理商: TSC2200IPWR
33
www.ti.com
TSC2200
SBAS191F
FIGURE 27. D/A Converter Configuration.
FIGURE 28. D/A Converter Output Current Range versus
RRNG Resistor Value.
OPERATION
D/A CONVERTER
The TSC2200 has an onboard 8-bit D/A converter, config-
ured as shown in Figure 27. This configuration yields a
current sink (A
OUT
) controlled by the value of a resistor
connected between the ARNG pin and ground. The D/A
converter has a control register that controls whether or not
the converter is powered up. The 8-bit data is written to the
D/A converter through the D/A converter data register.
This circuit is designed for flexibility in the output voltage at the
V
BIAS
point shown in Figure 27 to accommodate the widely
varying requirements for LCD contrast control bias. V+ can be
a higher voltage than the supply voltage for the TSC2200. The
only restriction is that the voltage on the A
OUT
pin can never go
above the absolute maximum ratings for the device, and
should stay above 1.5V for linear operation.
The D/A converter has an output sink range that is limited to
1mA. This range can be adjusted by changing the value of
RRNG shown in Figure 27. As this D/A converter is not
designed to be a precision device, the actual output current
range can vary as much as
±
20%. Furthermore, the current
output will change due to variations in temperature; the D/A
converter has a temperature coefficient of approximately
2
μ
A/
°
C. To set the full-scale current, RRNG can be deter-
mined from the graph shown in Figure 28.
For example, consider an LCD that has a contrast control
voltage V
BIAS
that can range from 2V to 4V, which draws
400
μ
A when used, and an available +5V supply. Note that
this is higher than the TSC2200 supply voltage, but it is within
the absolute maximum ratings.
The maximum V
BIAS
voltage is 4V, and this occurs when the
D/A converter current is 0, so only the 400
μ
A load current
I
LOAD
will be flowing from 5V to V
BIAS
. This means 1V will be
dropped across R
1
, so R
1
= 1V/400
μ
A = 2.5k
.
The minimum V
BIAS
is 2V, which occurs when the D/A
converter current is at its full scale value, I
MAX
. In this case,
5V
2V = 3V will be dropped across R
1
, so the current
through R
1
will be 3V/2.5K = 1.2mA. This current is
I
MAX
+ I
LOAD
= I
MAX
+ 400uA, so I
MAX
must be set to 800
μ
A.
Looking at Figure 28, this means that RRNG should be
around 1M
.
Since the voltage at the A
OUT
pin should not go below 1.5V,
this limits the voltage at the bottom of R
2
to be 1.5V minimum;
this occurs when the D/A converter is providing its maximum
current, I
MAX
. In this case, I
MAX
+ I
LOAD
flows through R
1
, and
I
MAX
flows through R
2
. Thus,
R
2
I
MAX
+ R
1
(I
MAX
+ I
LOAD
) = 5V
1.5V = 3.5V
(8)
We already have found R
1
= 2.5k
, I
MAX
= 800
μ
A,
I
LOAD
= 400
μ
A, so we can solve this for R
2
and find that it
should be 625
.
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10k
100k
1M
10M
100M
I
O
ARNG Resistor (
)
D/A Converter
V+
V
BIAS
A
OUT
ARNG
RRNG
R
2
R
1
8 Bits
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