參數(shù)資料
型號: TSC2100IDARG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO32
封裝: GREEN, PLASTIC, TSSOP-32
文件頁數(shù): 21/76頁
文件大?。?/td> 1143K
代理商: TSC2100IDARG4
TSC2100
SLAS378 NOVEMBER 2003
www.ti.com
28
D When PLL is enabled and D = 0, the following condition must be satisfied
80 MHz v MCLK
K
P
v 110 MHz
2MHz v MCLK
P
v 20 MHz
4 v J v 55
D When PLL is enabled and D ≠ 0, the following condition must be satisfied
80 MHz v MCLK
K
P
v 110 MHz
10 MHz v MCLK
P
v 20 MHz
4 v J v 11
Example 1:
For MCLK = 12 MHz and Fsref = 44.1 kHz
P = 1, K = 7.5264 J = 7, D = 5264
Example 2:
For MCLK = 12 MHz and Fsref = 48.0 kHz
P = 1, K = 8.192 J = 8, D = 1920
MONO AUDIO ADC
Analog Front End
The analog front end of the audio ADC consists of an analog MUX and a programmable gain amplifier (PGA). The MUX
can connect either the MICIN or AUX signal through the PGA to the ADC for audio recording. The TSC2100 also has an
option of choosing both MICIN and AUX as a differential input pair. The TSC2100 also includes a microphone bias circuit,
which can source up to 4 mA of current and is programmable to a 2 V or 2.5 V level. The bias block is powered down when
both the ADC and analog mixer blocks are powered down.
Because of the oversampling nature of the audio ADC and the integrated digital dicimation filtering, requirements for analog
antialiasing filtering are very relaxed. The TSC2100 integrates a second order analog antialiasing filter with 20-dB
attenuation at 1 MHz. This filter, combined with the digital decimal filter, provides sufficient antialiasing filtering without
requiring any external components.
The PGA allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with
an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-dB step every one or two ADC
output samples, depending on the register programming. This soft-stepping ensures that volume control changes occur
smoothly with no audible artifacts. Upon reset, the PGA gain defaults to a mute condition, and upon power down, the PGA
soft-steps the volume to mute before shutting down. A read-only flag (D0 control register 04H/Page2) is set whenever the
gain applied by PGA equals the desired value set by the register. The softstepping control can be disabled by
programming D15=1 in register 1DH of Page02. When soft stepping is enabled, the MCLK signal must be applied to the
part after the ADC power down register is written to ensure the soft-stepping to mute has completed. When the ADC power
down flag is no longer set, the MCLK signal can be shut down.
Delta-Sigma ADC
The analog-to-digital converter is a delta-sigma modulator with 128 times oversampling ratio. The ADC can support a
maximum output rate of 53 kHz.
Decimation Filter
The audio ADC includes an integrated digital decimation filter that removes high-frequency content and downsamples the
audio data from an initial sampling rate of 128 times Fs to the final output sampling rate of Fs. The decimation filter provides
a linear phase output response with a group delay of 17/Fs. The 3-dB bandwidth of the decimation filter extends to 0.45
Fs and scales with the sample rate (Fs)
相關(guān)PDF資料
PDF描述
TSC2100IDAR SPECIALTY CONSUMER CIRCUIT, PDSO32
TSC2100IDA SPECIALTY CONSUMER CIRCUIT, PDSO32
TSC2100IRHBR SPECIALTY CONSUMER CIRCUIT, PQCC32
TSC2100IRHB SPECIALTY CONSUMER CIRCUIT, PQCC32
TSC2100IDAG4 SPECIALTY CONSUMER CIRCUIT, PDSO32
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TSC2100IRHBRMULT1 制造商:Texas Instruments 功能描述: