參數(shù)資料
型號: TSC2008IYZGR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, BGA12
封裝: 2 X 1.50 MM, GREEN, DSBGA-12
文件頁數(shù): 20/40頁
文件大?。?/td> 1028K
代理商: TSC2008IYZGR
12-Bit Operation
8-Bit Operation
www.ti.com.......................................................................................................................................................... SBAS406B – JUNE 2008 – REVISED MARCH 2009
For 12-bit operation, sending the conversion result across the SPI bus takes 16 or 24 bus clocks (SCLK clock);
see Figure 31 and Figure 30. There is an additional SCLK to be added to accommodate the cycle overhead (time
between consecutive cycles) so that the total bus cycle time used for calculating the throughput is actually 17 or
25 bus clocks (SCLK clock), respectively. Using a TSC2046-compatible SDO output mode or an SDO-adjusted
output mode does not affect the transmission time.
Seven sample-and-conversions take (19 x 7) internal clocks to complete. The MAV filter loop requires 19 internal
clocks. For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 6. Because the
first acquisition cycle overlaps with the I/O cycle, four CCLKs must be deducted from the total CCLK cycles. The
total time required is (19 × 7 + 19) – 4 = 148 CCLKs plus I/O.
For 8-bit operation, sending the conversion result across the SPI bus takes 8, 16, or 24 bus clocks (SCLK clock);
see Figure 33, Figure 32, and Figure 30. There is an additional SCLK to be added to accommodate the cycle
overhead (time between consecutive cycles) so that the total bus cycle time used for calculating the throughput is
actually 9, 17, or 25 bus clocks (SCLK clock), respectively. Sending the conversion result takes 17 or 25 SCLKs
using 8-bit resolution and a TSC2046-compatible SDO output mode. If an SDO-adjusted output mode is used
with 8-bit resolution, it takes only 9 or 17 SCLKs to send the result back to host.
Seven sample-and-conversions take (16 x 7) internal clocks to complete. The MAV filter loop takes 19 internal
clocks. For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 6. Because the
first acquisition cycle is overlapped with the I/O cycle, four CCLKs must be deducted from the total CCLK cycles.
The total time required is (16 × 7 + 19) – 4 = 127 CCLKs plus I/O.
Table 6. Measurement Cycle Time Calculations(1)(2)
fSCLK = 100kHz (Period = 10s)
8-Bit
17 × 10
s + 127 × 322.6ns = 211.0s
12-Bit
25 × 10
s + 148 × 645.2ns = 345.5s
fSCLK = 1MHz (Period = 1s)
8-Bit
17 × 1
s + 127 × 322.6ns = 58.0s
12-Bit
25 × 1
s + 148 × 645.2ns = 120.5s
fSCLK = 2MHz (Period = 500ns)
8-Bit
17 × 500ns + 127 × 322.6ns = 49.5
s
12-Bit
25 × 500ns + 148 × 645.2ns = 108.0
s
fSCLK = 2.5MHz (Period = 400ns)
8-Bit
17 × 400ns + 127 × 322.6ns = 47.8
s
12-Bit
25 × 400ns + 148 × 645.2ns = 105.5
s
fSCLK = 4MHz (Period = 250ns)
8-Bit
17 × 250ns + 127 × 322.6ns = 45.2
s
12-Bit
25 × 250ns + 148 × 645.2ns = 101.7
s
fSCLK = 10MHz (Period = 100ns)
8-Bit
17 × 100ns + 127 × 322.6ns = 42.7
s
12-Bit
25 × 100ns + 148 × 645.2ns = 98.0
s
fSCLK = 16MHz (Period = 62.5ns)
8-Bit
17 × 62.5ns + 127 × 322.6ns = 42.0
s
12-Bit
25 × 62.5ns + 148 × 645.2ns = 97.1
s
fSCLK = 25MHz (Period = 40ns)
8-Bit
17 × 40ns + 127 × 322.6ns = 41.7
s
12-Bit
25 × 40ns + 148 × 645.2ns = 96.5
s
(1)
8-bit mode cycle time is calculated based on SDO-adjusted output mode.
(2)
CCLK period used for calculation is worst-case at 1.2V supply, 322.6ns.
Copyright 2008–2009, Texas Instruments Incorporated
27
Product Folder Link(s): TSC2008
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