參數(shù)資料
型號: TSB41AB2I
廠商: Texas Instruments, Inc.
英文描述: IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER
中文描述: 個IEEE 1394a - 2000雙端口電纜TRANSCEVER /仲裁者
文件頁數(shù): 15/50頁
文件大小: 662K
代理商: TSB41AB2I
SLLS418G
JUNE 2000
REVISED JANUARY 2003
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
D, CTL, LREQ
SYSCLK
Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms
td
D, CTL, LREQ
SYSCLK
Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms
APPLICATION INFORMATION
internal register configuration
There are 16 accessible internal registers in the TSB41AB3. The configuration of the registers at addresses 0h
through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the
paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected.
The selected page is set in base register 7h.
The configuration of the base registers is shown in Table 1, and corresponding field descriptions given in
Table 2. The base register field definitions are unaffected by the selected page number.
A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables)
is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.
Table 1. Base Register Configuration
Address
BIT POSITION
3
0
1
2
4
5
6
7
0000
Physical ID
R
CPS
0001
RHB
IBR
Gap_Count
0010
Extended (111b)
Rsvd
Num_Ports (0011b)
0011
PHY_Speed (010b)
Rsvd
Delay (0000b)
0100
LCtrl
C
Jitter (000b)
Pwr_Class
0101
RPIE
ISBR
CTOI
CPSI
STOI
PEI
EAA
EMC
0110
Reserved
0111
Page_Select
Rsvd
Port_Select
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