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參數(shù)資料
| 型號： | TSB12LV01BPZ |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 9/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV01BPZ |
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1 Overview
1.1
TSB12LV32 Description
The TSB12LV32 (GP2Lynx) is a high-performance general-purpose IEEE P1394a link-layer controller
(LLC) with the capability of transferring data between a host controller, the 1394 Phy-link interface, and
external devices connected to the data mover port (local bus interface). The 1394 Phy-link interface
provides the connection to the 1394 physical layer device and is supported by the LLC. The LLC provides
the control for transmitting and receiving 1394 packet data between the microcontroller interface and the
Phy-link interface via internal 2K byte FIFOs at rates up to 400 Mbit/s. The TSB12LV32 transmits and
receives correctly formatted 1394 packets, generates and detects the 1394 cycle start packets,
communicates transaction layer transmit requests to the Phy, and generates and inspects the 32-bit cyclic
redundancy check (CRC). The TSB12LV32 is capable of being cycle master (CM), isochronous resource
manager (IRM), bus manager, and supports reception of isochronous data on two channels.
The TSB12LV32 supports a direct interface to many microprocessors/microcontrollers including
programmable endian swapping. TSB12LV32 has a generic 16/8-bit host bus interface which includes
support for the ColdFire
microcontroller mode at rates up to 60 MHz. The microinterface may operate in
byte or word (16 bit) accesses. The data mover block in GP2Lynx is meant to handle an external memory
interface of large data blocks. The port can be configured to either transmit or receive data packets. The
packets can be either asynchronous, isochronous, or streaming data packets. Asynchronous or
isochronous receive packets will be routed to the DM port or the GRF via the receiver routing control logic.
The internal FIFO is separated into a transmit FIFO and a receive FIFO each of 517 quadlets (2 Kbytes).
Asynchronous packets may be transmitted from the DM port or the internal FIFO. If there is contention the
FIFO has priority and will be transmitted first.
The LLC also provides the capability to receive status information from the physical layer device and to
access the physical layer control and status registers by the application software.
ColdFire is a trademark of Motorola, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB12LV26-EP | 672-pin FineLine BGA |
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01PZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB12LV21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER |
| TSB12LV21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE |
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