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參數(shù)資料
| 型號(hào)： | TSA5055T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | 2.65 GHz bidirectional I2C-bus controlled synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2650 MHz, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SOP-16 |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大?。?/td> | 101K |
| 代理商： | TSA5055T |
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1999 Aug 11
6
Philips Semiconductors
Product specification
2.65 GHz bidirectional I
2
C-bus controlled
synthesizer
TSA5055T
Table 2
Read data format (see notes 1 to 5)
Notes
1.
2.
3.
4.
5.
POR: Power-on reset flag (POR = 1 on power-on).
FL: in-lock flag (FL = 1 when the loop is phase-locked).
I2, I1 and I0: digital information for I/O ports P7, P5 and P4 respectively.
A2, A1 and A0: digital outputs of the 5-level ADC. Accuracy is
1
2
LSB (see Table 4).
MSB is transmitted first.
Bits I2, I1 and I0 represent the status of the I/O ports P7, P5 and P4, respectively. A logic ‘0’ indicates a LOW level and
a logic ‘1’ a HIGH level (TTL levels). A built-in 5-level ADC is available at I/O port P6. This ADC can be used to feed AFC
information to the controller from the IF section of the receiver, as shown in Fig.4. The relationship between bits A2, A1,
A0 and the input voltage at port P6 is given in Table 4.
Table 3
Address selection
Address selection
; see Table 3
The module address contains programmable address bits (MA1 and MA0), which offer the possibility of having several
synthesizers (up to three) in one system. The relationship between MA1 and MA0 and the input voltage at port P3 is
given in Table 3.
Table 4
ADC levels
BYTE
MSB
DATA BYTE
LSB
COMMAND
Address
Status byte
1
1
0
I2
0
I1
0
I0
MA1
A2
MA0
A1
1
A
byte 1
byte 2
POR
FL
A0
MA1
MA0
VOLTAGE APPLIED ON PORT P3
0
0
1
1
0
1
0
1
0 to 0.1V
CC
always valid
0.4V
CC
to 0.6V
CC
0.9V
CC
to 13.5 V
A2
A1
A0
VOLTAGE APPLIED ON PORT P6
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0.6V
CC
to V
CC
0.45V
CC
to 0.6V
CC
0.3V
CC
to 0.45V
CC
0.15V
CC
to 0.3V
CC
0 to 0.15V
CC
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