參數(shù)資料
型號(hào): TSA1005-40IF
元件分類: ADC
英文描述: Analog to Digital Converter
中文描述: 模數(shù)轉(zhuǎn)換器
文件頁數(shù): 13/19頁
文件大小: 194K
代理商: TSA1005-40IF
TSA1005-40
13/19
analog input while VREFM is connected to
ground; weachieve a 2Vpp differential amplitude.
Figure 8 :
DC-coupled 2Vpp analog input
Dynamic characteristics, while not being as
remarkable as for differential configuration, are
still of very good quality.
Clock input
The TSA1005-40 performance is very dependant
on your clock input accuracy, in terms of aperture
jitter; the use of low jitter crystal controlled
oscillator is recommended.
The duty cycle must be between 45% and 55%.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is recommended to always keep the circuit
clocked, even at the lowest specified sampling
frequency of 0.5Msps, before applying the supply
voltages.
Power consumption
So as to optimize both performance and power
consumption of the TSA1005-40 according the
sampling frequency, a resistor is placed between
IPOL and the analog Ground pins. Therefore, the
total dissipation is adjustable from 35Msps up to
50Msps.
The TSA1005-40 will combine highest perfor-
mances and lowest consumption at 40Msps when
Rpol is equal to 30k
. This value is nevertheless
dependant on application and environment.
At lower sampling frequency range, this value of
resistor may be adjusted in order to decrease the
analog
current
without
dynamic performances.
any
degradation
of
The figure 9 sums up the relevant data.
Figure 9 :
analog current consumption
optimization depending on Rpol value
APPLICATION
Layout precautions
To usethe ADC circuits inthe best manner at high
frequencies, some precautions have to be taken
for power supplies:
- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is recommended for high speed circuit
applications to provide low inductance and low
resistance common return.
The separation of the analog signal from the
digital part is mandatory to prevent noise from
coupling
onto
the
input
compromise is to connect from one part AGND,
DGND, GNDBI in a common point whereas
GNDBE must be isolated. Similarly, the power
supplies AVCC, DVCC and VCCBI must be
separated from the VCCBE one.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.
- Proper termination of all inputs and outputs must
be incorporated with output termination resistors;
then the amplifier load will be only resistive and
the stability of the amplifier will be improved. All
leads must be wide and as short as possible
especially for the analog input inorder to decrease
parasitic capacitance and inductance.
- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
the output changes. To minimize this output
signal.
The
best
TSA1005
VINB
VIN
INCM
330pF
4.7uF
10nF
Analog
DC
AC+DC
VREFP
VREFM
VREFP-VREFM = 1 V
0
10
20
30
40
50
60
70
80
90
100
5
15
25
35
45
55
Fs (MHz)
I
0
50
100
150
200
250
R
RPOL
ICCA
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