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參數(shù)資料
| 型號： | TSA0801CFT |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT, 40MSPS, 40mW A/D CONVERTER |
| 中文描述： | 8位，40MSPS，40mW的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 222K |
| 代理商： | TSA0801CFT |
TSA0801
16/20
performances when configured as shown on
Figure 8.
Figure 8 :
External reference setting
At 15Msps sampling frequency, 1MHz input fre-
quency and -1dBFS amplitude signal, perfor-
mances can be improved of up to 2dBc on SFDR
and 0.3dB on SINAD. At 40Msps sampling fre-
quency, 1MHz inputfrequency and -1dBFS ampli-
tude signal, performances can be improved of up
to 1dBc on SFDR and 0.6dB on SINAD.
This canbe very helpful for example for multichan-
nel application to keep a good matching among
the sampling frequency range.
Clock input
The quality of your converter is very dependant on
your clock input accuracy, in terms of aperture jit-
ter; the use of low jitter crystal controlled oscillator
is recommended.
The duty cycle must be between 45% and 55%.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise modu-
lation at the output.
It is recommended to always keep the circuit
clocked, even at the lowest specified sampling
frequency of 0.5Msps, before applying the supply
voltages.
Power consumption optimization
The internal architecture of the TSA0801 enables
to optimize the power consumption according to
the sampling frequency of the application. For this
purpose, a resistor is placed between IPOL and
the analog Ground pins.
The TSA0801 will combine highest performances
and lowest consumption at 40Msps when Rpol is
equal
to 18k
.
At lower sampling frequency range (< 10Msps),
this value of resistor may be adjusted in order to
decrease
the
analog
degradation of dynamic performances.
As an example, 10mW total power consumption is
achieved at 5 Msps with Rpol equel to 390k
.
The table below sums up the relevant data.
current
without
any
Total power consumption optimization
depending on Rpol value
Fs (Msps)
5
Rpol (
k
)
390
Optimized
power (mW)
Layout precautions
To usethe ADC circuits inthe best manner at high
frequencies, some precautions have to be taken
for power supplies:
- First of all, the implementation of 4 separate
proper supplies and ground planes (analog, digi-
tal, internal and external buffer ones) on the PCB
is mandatory for high speed circuit applications to
provide low inductance and low resistance com-
mon return.
The separation of the analog signal from the digi-
tal part is essential to prevent noise from coupling
onto the input signal.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion. - Proper termination of all
inputs and outputs must be incorporated with
output termination resistors; then the amplifier
load will be only resistive and the stability of the
amplifier will be improved. All leads must be wide
and as short as possible especially for the analog
input in order to decrease parasitic capacitance
and inductance.
- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
the output changes. To minimize this output
capacitance, buffers or latches close to the output
pins will relax this constraint.
- Choose component sizes as small as possible
(SMD).
1k
TSA0801
VINB
VIN
VREFM
VREFP
external
reference
TS821
VCCA
330pF
470nF
10nF
15
40
25
25
25
35
40
18
40
10
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