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參數(shù)資料
| 型號： | TS8388BMFSB/QNB2 |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 18/42頁 |
| 文件大?。?/td> | 1307K |
| 代理商： | TS8388BMFSB/QNB2 |
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Product Specification
TS8388BFS
6. DEFINITION OF TERMS
(BER)
Bit Error Rate
Probability to exceed a specified error threshold for a sample. An error code is a code that differs
by more than +/- 4 LSB from the correct code.
(BW)
Full power input
bandwidth
Analog input frequency at which the fundamental component in the digitally reconstructed output
has fallen by 3 Db with respect to its low frequency value (determined by FFT analysis) for input
at Full Scale.
(SINAD)
Signal to noise and
distortion ratio
Ratio expressed in Db of the RMS signal amplitude, set to 1Db below Full Scale, to the RMS
sum of all other spectral components, including the harmonics except DC.
(SNR)
Signal to noise ratio
Ratio expressed in Db of the RMS signal amplitude, set to 1Db below Full Scale, to the RMS
sum of all other spectral components excluding the five first harmonics.
(THD)
Total harmonic
distorsion
Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS value
of the measured fundamental spectral component.
(SFDR)
Spurious free dynamic
range
Ratio expressed in Db of the RMS signal amplitude, set at 1Db below Full Scale, to the RMS
value of the next highest spectral component (peak spurious spectral component). SFDR is the
key parameter for selecting a converter to be used in a frequency domain application ( Radar
systems, digital receiver, network analyzer ….). It may be reported in dBc (i.e., degrades as
signal levels is lowered), or in Dbfs (i.e. always related back to converter full scale).
(ENOB)
Effective Number Of Bits
Where A is the actual input amplitude and V
is the full scale range of the ADC under test
(DNL)
Differential non
linearity
The Differential Non Linearity for an output code i is the difference between the measured step
size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum
value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there are no
missing output codes and that the transfer function is monotonic.
(INL)
Integral non linearity
The Integral Non Linearity for an output code i is the difference between the measured input
voltage
at
which
the
transition
occurs
and
the
ideal
value
of
this
transition.
INL (i) is expressed in LSBs, and is the maximum value of all
|INL (i)|.
(DG)
Differential gain
The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full
Scale peak to peak amplitude. FIN = 5 MHz. (TBC)
(DP)
Differential phase
Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full Scale
peak to peak amplitude. FIN = 5 MHz. (TBC)
(TA)
Aperture delay
Delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing point),
and the time at which (VIN,VINB) is sampled.
(JITTER)
Aperture uncertainty
Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew
rate of the signal at the sampling point.
(TS)
Settling time
Time delay to achieve 0.2 % accuracy at the converter output when a 80% Full Scale step
function is applied to the differential analog input.
(ORT)
Overvoltage recovery
time
Time to recover 0.2 % accuracy at the output, after a 150 % full scale step applied on the input is
reduced to midscale.
(TOD)
Digital data
Output delay
Delay from the falling edge of the differential clock inputs (CLK,CLKB) (zero crossing point) to
the next point of change in the differential output data (zero crossing) with specified load.
(TD1)
Time delay from Data to
Data Ready
Time delay from Data transition to Data ready.
(TD2)
Time delay from Data
Ready to Data
General expression is TD1 = TC1 + TDR – TOD with TC = TC1 + TC2 = 1 encoding clock
period.
(TC)
Encoding clock period
TC1 = Minimum clock pulse width (high) TC = TC1 + TC2
TC2 = Minimum clock pulse width (low)
(TPD)
Pipeline Delay
Number of clock cycles between the sampling edge of an input data and the associated output
data being made available, (not taking in account the TOD). For the TS8388BFS the TPD is 4
clock periods.
(TRDR)
Data Ready reset delay
Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB)
and the reset to digital zero transition of the Data Ready output signal (DR).
(TR)
Rise time
Time delay for the output DATA signals to rize from 20% to 80% of delta between low level and
SINAD - 1.76 + 20 log (A/V/2)
ENOB =
6.02
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