參數(shù)資料
型號: TS8388BMF
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝: CERAMIC, QFP-68
文件頁數(shù): 23/44頁
文件大?。?/td> 850K
代理商: TS8388BMF
3
Preliminary Beta-Site
Specification
TS8388BF
1.
SIMPLIFIED BLOCK DIAGRAM
G=2
T/H
G=1
T/H
G=1
CLOCK
BUFFER
RESISTOR
CHAIN
ANALOG
ENCODING
BLOCK
INTERPOLATION
STAGES
REGENERATION
LATCHES
ERROR CORRECTION &
DECODE LOGIC
OUTPUT LATCHES &
BUFFERS
4
5
4
5
8
VIN,VINB
CLK, CLKB
GAIN
DRRB DR,DRB
GORB
DATA,DATAB
OR,ORB
MASTER/SLAVE TRACK & HOLD AMPLIFIER
2.
FUNCTIONAL DESCRIPTION
The TS8388BF is an 8 bit 1GSPS ADC based on an advanced high speed bipolar technology (B6HF from SIEMENS) featuring a cutoff frequency of
25 GHz.
The TS8388BF includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry.
Successive banks of
latches are regenerating the analog residues into logical data before entering an error correction circuitry and a
resynchronization stage followed by 75
differential output buffers.
The TS8388BF works in fully differential mode from analog inputs up to digital outputs.
The TS8388BF features a full power input bandwidth of 1.5 GHz.
Control pin GORB is provided to select either Gray or Binary data output format.
Gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8388BF.
The TS8388BF uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation
tolerance (no performance drift measured at 150kRad total dose).
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