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參數(shù)資料
| 型號(hào)： | TS8388BCFS |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | ADC 8-bit 1 GSPS |
| 中文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | HEAT SPREADER, CERAMIC, QFP-68 |
| 文件頁數(shù)： | 13/57頁 |
| 文件大小： | 1276K |
| 代理商： | TS8388BCFS |
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13
TS8388B
2144C–BDC–04/03
Package
Description
Pin Description
Note:
1. The common mode level of the output buffers is 1.2V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0V (ground).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.
If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the posi-
tive digital supply level in the same proportion in order to spare power dissipation.
Table 7.
TS8388BGL Pin Description (CBGA68 package)
Symbol
Pin number
Function
GND
A2, A5, B1, B5, B10, C2, D2, E1, E2, E11,
F1, F2, G11, K2, K3, K4, K5, K10, L2, L5
Ground pins.
To be connected to external ground plane.
V
CC
A4, A6, B2, B4, B6, H1, H2, L6, L7
+5V positive supply.
V
EE
A3, B3, G1, G2, J1, J2
5V analog negative supply.
DV
EE
F10, F11
-5V digital negative supply.
V
IN
L3
In phase (+) analog input signal of the Sample and Hold
differential preamplifier.
V
INB
L4
Inverted phase (-) of ECL clock input signal (CLK).
CLK
C1
In phase (+) ECL clock input signal. The analog input is
sampled and held on the rising edge of the CLK signal.
CLKB
D1
Inverted phase (-) of ECL clock input signal (CLK).
B0, B1, B2, B3, B4,
B5, B6, B7
A8, A9, A10, D10, H11, J11, K9, K8
In phase (+) digital outputs.
B0 is the LSB. B7 is the MSB.
B0B, B1B, B2B, B3B,
B4B, B5B, B6B, B7B
B7, B8, B9, C11, G10, H10, L10, L9
Inverted phase (-) digital outputs.
B0B is the inverted LSB. B7B is the inverted MSB.
OR
K7
In phase (+) Out of Range Bit. Out of Range is high on the
leading edge of code 0 and code 256.
ORB
L8
Inverted phase (+) Out of Range Bit (OR).
DR
E10
In phase (+) output of Data Ready Signal.
DRB
D11
Inverted phase (-) output of Data Ready Signal (DR).
GORB
A7
Gray or Binary select output format control pin.
- Binary output format if GORB is floating or V
CC
.
- Gray output format if GORB is connected at ground (0V).
GAIN
K6
ADC gain adjust pin. The gain pin is by default grounded, the
ADC gain transfer fuction is nominally close to one.
DIOD/DRRB
K1
Die function temperature measurement pin and
asynchronous data ready reset active low, single-ended ECL
input.
V
PLUSD
B11, C10, J10, K11
+2.4V for LVDS output levels otherwise to GND
(2)
.
NC
A1, A11, L1, L11
Not connected.
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