參數(shù)資料
型號(hào): TS8388BCFS9QB3ZB9
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝: CERAMIC, QFP-68
文件頁數(shù): 43/43頁
文件大小: 825K
代理商: TS8388BCFS9QB3ZB9
TS8388BFS
9/42
Preliminary Beta Site
3.4.
TIMING DIAGRAMS
TC1
TC2
TA= 250 ps TBC
X
N+1
X
N+2
X
N+3
N
Figure 1 : TS8388B TIMING DIAGRAM
( 1 GSPS CLOCK RATE )
Data Ready Reset , Clock held at LO W level
DIGITAL
OUTPUTS
(V
IN,
V
INB
)
Data Ready
(DR, DRB)
(CLK, CLKB)
X
N+5
TD1=TC1+TDR-TOD
= TC1-40 ps = 460 ps
ps
DATA
N-4
DATA
N-3
DATA N
DATA
N-1
DATA
N-2
TC=1000 ps
X
N+4
TOD = 1360 ps
1360 ps
DRRB
1ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
1000 ps
TRDR = 920 ps
N-1
TD2 = TC2+TOD-TDR
= TC2+40ps = 540 ps
TDR = 1320 ps
DATA
N-5
DATA
N+1
TC1
TC2
TA= 250ps TBC
X
N+1
X
N+2
X
N+3
N
Figure 2 : TS8388B TIMING DIAGRAM
( 1 GSPS CLOCK RATE )
Data Ready Reset , Clock held at HIGH level
DIGITAL
OUTPUTS
(V
IN,
V
INB
)
Data Ready
(DR, DRB)
(CLK, CLKB)
X
N+5
TD1=TC1+TDR-TOD
= TC1-40 ps = 460 ps
DATA
N-4
DATA
N-3
DATA N
DATA
N-1
DATA
N-2
TC = 1000 ps
X
N+4
TOD = 1360 ps
1360 ps
DRRB
1ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
1000 ps
TRDR = 920ps
N-1
TD2 = TC2+TOD-TDR
= TC2+40ps = 540 ps
TDR = 1120 ps
DATA
N-5
DATA
N+1
相關(guān)PDF資料
PDF描述
TS8388BCFS9QC2ZB9 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
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TS8388BMFS9QC1ZB9 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
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