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參數(shù)資料
| 型號(hào)： | TS8388BCFB/Q |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁(yè)數(shù)： | 47/47頁(yè) |
| 文件大?。?/td> | 1230K |
| 代理商： | TS8388BCFB/Q |
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9
TS8388BF
2144A–BDC–04/02
Timing Diagrams
Figure 2. TS8388BF Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at LOW Level
Figure 3. TS8388BF Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at HIGH Level
TC1
TC2
TA = 250 ps TBC
X
N+1
X
N+2
X
N+3
N
DIGITAL
OUTPUTS
(VIN, VINB)
Data Ready
(DR, DRB)
(CLK, CLKB)
X
N+5
N-4
N-3
N
N-2
N-1
TC = 1000 ps
X
N+4
TOD = 1360 ps
1360 ps
DRRB
1 ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
1000 ps
TRDR = 720 ps
N-1
TD2 = TC2+TOD-TDR
= TC2+40 ps = 540 ps
TDR = 1320 ps
DATA
N-5
N+1
TD1 = TC1+TDR-TOD
= TC1-40 ps = 460 ps
TC1
TC2
TA = 250 ps TBC
N+1
N+2
N
DIGITAL
OUTPUTS
(VIN, VINB)
Data Ready
(DR, DRB)
(CLK, CLKB)
N+5
N-4
N-3
N
N-1
N-2
TC = 1000 ps
N+4
TOD = 1360 ps
1360 ps
DRRB
1 ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
TRDR = 720 ps
N-1
TD2 = TC2+TOD-TDR
= TC2+40 ps = 540 ps
TDR = 1320 ps
DATA
N-5
N+1
1000 ps
X
TD1 = TC1+TDR-TOD
= TC1-40 ps = 460 ps
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| TS8388BVFSB/Q | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
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| TS8388BMFB/Q | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS8388BCFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A/D CONVERTER |
| TS8388BCGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMF | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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