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參數(shù)資料
| 型號： | TS8388B |
| 廠商： | Atmel Corp. |
| 元件分類： | ADC |
| 英文描述： | ADC 8-bit 1 GSPS |
| 中文描述： | ADC的8位1 GSPS的 |
| 文件頁數(shù)： | 15/57頁 |
| 文件大小： | 1276K |
| 代理商： | TS8388B |
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15
TS8388B
2144C–BDC–04/03
Notes:
1. Following pin numbers 37 (CLK), 40 (CLKB), 54 (V
IN
) and 57 (V
INB
) have to be connected to GND through a 50
resistor as
close as possible to the package (50
termination preferred option).
2. The common mode level of the output buffers is 1.2V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0V (ground).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.
If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the posi-
tive digital supply level in the same proportion in order to spare power dissipation.
Table 8.
TS8388BF/TS8388BFS Pin Description (CQFP68 package)
Symbol
Pin number
Function
GND
5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51,
52, 53, 58, 59
Ground pins.
To be connected to external ground plane.
V
PLUSD
1, 2, 16, 17, 18, 68
Digital positive supply (0V for ECL compatibility, 2.4V for
LVDS compatibility).
(2)
V
CC
26, 29, 32, 33, 46, 47, 61
+5V positive supply.
V
EE
30, 31, 44, 45, 48
-5V analog negative supply.
DV
EE
8, 9, 10
-5V digital negative supply.
V
IN
54
(1)
, 55
In phase (+) analog input signal of the Sample and Hold
differential preamplifier.
V
INB
56, 57
(1)
Inverted phase (-) of analog input signal (V
IN
).
CLK
37
(1)
, 38
In phase (+) ECL clock input signal. The analog input is
sampled and held on the rising edge of the CLK signal.
CLKB
39, 40
(1)
Inverted phase (-) of ECL clock input signal (CLK).
D0, D1, D2, D3, D4,
D5, D6, D7
23, 21, 19, 14, 6, 3, 66, 64
In phase (+) digital outputs.
B0 is the LSB. B7 is the MSB.
D0B, D1B, D2B, D3B,
D4B, D5B, D6B, D7B
24, 22, 20, 15, 7, 4, 67, 65
Inverted phase (-) digital outputs.
B0B is the inverted LSB. B7B is the inverted MSB.
OR
62
In phase (+) Out of Range Bit. Out of Range is high on the
leading edge of code 0 and code 256.
ORB
63
Inverted phase (+) Out of Range Bit (OR).
DR
11
In phase (+) output of Data Ready Signal.
DRB
12
Inverted phase (-) output of Data Ready Signal (DR).
GORB
25
Gray or Binary select output format control pin.
- Binary output format if GORB is floating or V
CC
.
- Gray output format if GORB is connected at ground (0V).
GAIN
60
ADC gain adjust pin.
DIOD/DRRB
49
This pin has a double function (can be left open or grounded
if not used):
- DIOD: die junction temperature monitoring pin.
- DRRB: asynchronous data ready reset function.
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