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TS823/824/825 Series
Microprocessor Supervisory Circuit
with Watchdog Timer & Manual Reset
2/8
Version: B07
Electrical Specifications
(Ta = 25
o
C, unless otherwise noted)
Parameter
Input Supply Voltage
Supply Current
WDI and MRB unconnected
TS823/824/825CX5A
TS823/824/825CX5B
TS823/824/825CX5D
TS823/824/825CX5E
TS823/824/825CX5F
TS823/824/825CX5G
TS823/824/825CX5H
RESET Output Voltage Low
Vdd<V
TH(MIN),
I
SINK
=1.2mA,
(RESET) Output Voltage High
Vdd>
VTH(MAX),
I
SOURCE
=0.5mA
Vdd to Reset Delay
Vdd =V
TH
- 100mV
Reset Active Timeout Period
Ta=-40
o
C ~+85
o
C
Watchdog Timeout Period
WDI Pulse Width
Conditions
Symbol
Vdd
Idd
Min
1.0
--
4.56
4.31
3.03
2.89
2.59
2.28
2.15
--
0.8 Vdd
--
140
1120
50
--
0.8 Vdd
-15
--
--
0.8 Vdd
1
--
--
80
1.0
Typ
--
3
4.63
4.38
3.08
2.93
2.63
2.32
2.19
--
--
40
210
1760
--
--
--
-8
8
--
--
--
100
500
--
--
Max
5.5
10
4.7
4.45
3.13
2.97
2.67
2.36
2.23
0.5
--
--
280
2400
--
0.7
--
0.7
15
0.7
--
--
--
--
120
5.5
Unit
V
uA
Reset Threshold
V
TH
V
V
OL
V
OH
T
D1
T
D2
T
WD
T
WDI
W
DIIL
W
DIIH
I
IL
I
IH
M
RIL
M
RIH
T
WMR
T
DMR
V
CC
V
V
uS
mS
mS
nS
V
V
uA
uA
V
V
uS
nS
nS
K
Ω
V
WDI Input Threshold
Vdd = V
TH
x 1.2
W
DI
=0V
W
DI
=Vdd = 5V
WDI Input Current
MR Input Threshold
Vdd=V
TH
x 1.2
MR Pulse Width
MR Noise Immunity
MR to Reset Delay
MR Pull Up Resistance
Input Supply Voltage
Pulse width with no reset
Vdd = V
TH
- 100mV
Ta=-40
o
C~+85
o
C
Detail Description
Pin Function
Pin Name
Reset
GND
(Reset)
Pin Description
Active Low
Ground
Active High
This pin is active low. Pulling this pin low to forces a reset. After a low to high transition reset remains
asserted for exactly one reset timeout period. This pin is internally pulled high. If this function is unused
then float this pin or tie it to Vdd.
Watch Dog Input. Any transition on this pin will reset the Watch Dog timer. If this pin remains high or
low for longer than the Watch Dog interval then a reset is asserted. Float or tri-state this pin to disable
the Watch Dog feature.
Positive power supply. A reset is asserted after this voltage drops below a predetermined level. After
Vdd rises above that level reset remains asserted until the end of the reset timeout period.
MR
WDI
Vdd